Patents by Inventor Nobuji Kobayashi

Nobuji Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8722512
    Abstract: The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 13, 2014
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Nobuji Kobayashi, Tetsuya Yamada
  • Publication number: 20100159670
    Abstract: The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 24, 2010
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Nobuji KOBAYASHI, Tetsuya Yamada
  • Patent number: 7595224
    Abstract: In a method for manufacturing a light detector that is provided with an apertured part for incident light on an upper structural layer stack laminated on a semiconductor substrate, a polyimide film, which is applied in order to protect a silicon-nitride film on an upper surface of the upper structural layer stack, is properly removed from the apertured part, allowing, e.g., the intensity of light incident within the apertured part to be made uniform. A smoothing film 140 is applied to the surface of the upper structural layer stack 86, smoothly covering corner parts 142 on the aperture edge of the apertured part 116. The smoothing film 140 is etched and the corner parts 142 that are exposed on the aperture edge, where the smoothing film 140 is thin, are removed by the etching. The aperture edge of the apertured part 116 is thereby enlarged. After the smoothing film 140 has been detached, a polyimide film is applied.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: September 29, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Nobuji Kobayashi
  • Publication number: 20090085168
    Abstract: When a photoresist or the like is spin-coated on a semiconductor chip comprising a seal ring is formed, striation due to corners of the seal ring is suppressed. A wiring metal layer and a contact are layered, and a seal structure (28) that surrounds an element forming region (22) on a semiconductor chip (20) is formed. A planar shape of the seal ring structure (28) has shape that is, at a basic level, a rectangle corresponding with the shape of the semiconductor chip (20), but with cutoffs present on corner parts (60) of the rectangle. Specifically, the seal ring structure (28) is disposed along a periphery of a rectangle having corner cutoffs.
    Type: Application
    Filed: September 18, 2008
    Publication date: April 2, 2009
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Nobuji Kobayashi, Isamu Tomizawa
  • Publication number: 20070202629
    Abstract: In a method for manufacturing a light detector that is provided with an apertured part for incident light on an upper structural layer stack laminated on a semiconductor substrate, a polyimide film, which is applied in order to protect a silicon-nitride film on an upper surface of the upper structural layer stack, is properly removed from the apertured part, allowing, e.g., the intensity of light incident within the apertured part to be made uniform. A smoothing film 140 is applied to the surface of the upper structural layer stack 86, smoothly covering corner parts 142 on the aperture edge of the apertured part 116. The smoothing film 140 is etched and the corner parts 142 that are exposed on the aperture edge, where the smoothing film 140 is thin, are removed by the etching. The aperture edge of the apertured part 116 is thereby enlarged. After the smoothing film 140 has been detached, a polyimide film is applied.
    Type: Application
    Filed: February 20, 2007
    Publication date: August 30, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Nobuji Kobayashi
  • Publication number: 20060131663
    Abstract: In a transistor, trenches are formed between each of a source region and a drain region and a channel region under the gate electrode at the position sandwiched by them. Ion implantation of impurity is carried out on the surface of the trench to form a low-concentration doped region. When the trench 50 is formed by etching, a projection 70 remains on the bottom thereof. Photoresist 86 is spin-coated on the principal surface of the semiconductor substrate where the trench 50 is formed. An opening for the photoresist 86 is installed at the part corresponding to the trench 50 and, using the photoresist 86 as a mask, ion implantation for the formation of a low-concentration doped region is performed. As a result of formation of a projection 70 in the trench, non-uniformity of film thickness of the photoresist in the trench is reduced.
    Type: Application
    Filed: December 9, 2005
    Publication date: June 22, 2006
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Nobuji Kobayashi