Patents by Inventor Nobukazu Murata
Nobukazu Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958225Abstract: A molding injection pressure and a molding clamping force are determined in advance to obtain a parting opening amount, which is a predetermined gap, between a movable mold and a fixed mold of a mold during injection filling.Type: GrantFiled: December 9, 2019Date of Patent: April 16, 2024Assignee: NISSEI PLASTIC INDUSTRIAL CO., LTD.Inventors: Hozumi Yoda, Nobukazu Kasuga, Hirofumi Murata
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Patent number: 10861510Abstract: A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.Type: GrantFiled: May 20, 2019Date of Patent: December 8, 2020Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Nobukazu Murata
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Publication number: 20190371375Abstract: A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.Type: ApplicationFiled: May 20, 2019Publication date: December 5, 2019Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Nobukazu MURATA
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Patent number: 10446568Abstract: The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.Type: GrantFiled: November 13, 2018Date of Patent: October 15, 2019Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Nobukazu Murata
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Patent number: 10310939Abstract: On the basis of data addresses indicative of write bit positions of each of the write data pieces in each of blocks, write page addresses indicative of pages having each of the write data pieces written thereto in each of the blocks are detected. At least one write data piece is incorporated into each of the page data pieces indicated by the write page addresses among k page data pieces corresponding to the k pages, the page data pieces having the write data pieces incorporated therein are used as page data pieces, and an error-correction encoding process is applied to each of the write page data pieces to obtain encoded write data pieces. Then, a voltage based on the encoded write data pieces is applied to each of the memory cells belonging to the pages indicated by the write page addresses.Type: GrantFiled: May 13, 2016Date of Patent: June 4, 2019Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Patent number: 10298120Abstract: A charge pump circuit includes a first capacitor and a second capacitor to which respective pulse signals are input; a first transistor including a source connected to a voltage input terminal, a drain connected to the first capacitor and a gate connected to the second capacitor; a second transistor including a source connected to the voltage input terminal, a drain connected to the second capacitor and a gate connected to the first capacitor; and a potential fixing circuit provided between a first node that is a connection node of the first transistor and the first capacitor, and a second node that is a connection node of the second transistor and the second capacitor. The potential fixing circuit fixes a potential of the first node to a potential according to a potential of the second node.Type: GrantFiled: December 11, 2017Date of Patent: May 21, 2019Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Nobukazu Murata
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Publication number: 20190081056Abstract: The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventor: NOBUKAZU MURATA
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Patent number: 10157931Abstract: The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.Type: GrantFiled: September 15, 2017Date of Patent: December 18, 2018Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Nobukazu Murata
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Publication number: 20180166985Abstract: The present disclosure provides a charge pump circuit including: a first capacitor and a second capacitor to which pulse signal are input; a first transistor including a source connected to a voltage input terminal, a drain connected to the first capacitor and a gate connected to the second capacitor; a second transistor including a source connected to the voltage input terminal, a drain connected to the second capacitor and a gate connected to the first capacitor; and a potential fixing circuit provided between a first node that is a connection node of the first transistor and the first capacitor, and a second node that is a connection node of the second transistor and the second capacitor, the potential fixing circuit fixing a potential of the first node to a potential according to a potential of the second node.Type: ApplicationFiled: December 11, 2017Publication date: June 14, 2018Inventor: NOBUKAZU MURATA
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Publication number: 20180083023Abstract: The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.Type: ApplicationFiled: September 15, 2017Publication date: March 22, 2018Inventor: NOBUKAZU MURATA
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Publication number: 20160335157Abstract: On the basis of data addresses indicative of write bit positions of each of the write data pieces in each of blocks, write page addresses indicative of pages having each of the write data pieces written thereto in each of the blocks are detected. At least one write data piece is incorporated into each of the page data pieces indicated by the write page addresses among k page data pieces corresponding to the k pages, the page data pieces having the write data pieces incorporated therein are used as page data pieces, and an error-correction encoding process is applied to each of the write page data pieces to obtain encoded write data pieces. Then, a voltage based on the encoded write data pieces is applied to each of the memory cells belonging to the pages indicated by the write page addresses.Type: ApplicationFiled: May 13, 2016Publication date: November 17, 2016Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Nobukazu MURATA
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Patent number: 8873312Abstract: The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.Type: GrantFiled: May 21, 2013Date of Patent: October 28, 2014Assignee: Lapis Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Publication number: 20130286755Abstract: The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.Type: ApplicationFiled: May 21, 2013Publication date: October 31, 2013Inventor: Nobukazu MURATA
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Patent number: 8456944Abstract: The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.Type: GrantFiled: February 22, 2011Date of Patent: June 4, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Patent number: 8441851Abstract: The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.Type: GrantFiled: February 23, 2011Date of Patent: May 14, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Patent number: 8331181Abstract: A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting one of the main bit lines connected to the memory cell to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the main bit line to a charging/discharging voltage source for setting at a specific voltage.Type: GrantFiled: November 26, 2010Date of Patent: December 11, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Patent number: 8203887Abstract: The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current.Type: GrantFiled: June 23, 2010Date of Patent: June 19, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Patent number: 8189405Abstract: A data readout circuit including a 1st PMOS transistor operating in saturation and including a source connected to a power supply, a drain connected to an input terminal a memory cell, and a gate connected to a 1st bias voltage; a 2nd PMOS transistor including a source connected to the drain of the 1st PMOS transistor, a drain connected to an output terminal, and a gate connected to a 2nd bias voltage; a 1st NMOS transistor including a drain connected to the drain of the 2nd PMOS transistor, a source grounded, and a gate connected to a 3rd bias voltage; and a bias voltage section causing the 2nd PMOS transistor to operate in saturation, and supplying the 2nd bias voltage adjusted so as to keep a reference voltage of the input terminal at a junction point between the drain and the source of the 1st and 2nd PMOS transistors respectively.Type: GrantFiled: July 16, 2009Date of Patent: May 29, 2012Assignee: OKI Semiconductor Co., Ltd.Inventors: Nobukazu Murata, Katsuaki Matsui
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Patent number: 8040195Abstract: A current source device that cuts off an output current when stopped and obtains a desired output current upon start-up includes a first circuit having a first FET and resistors in series, a second circuit having second and third FETs in series with a point between the second and third FETs and a gate of the third FET connected, a drive circuit supplying a common drive voltage to gates of the first and second FETs, and first and second current source circuits responsive to first and second drive voltages that are gate voltages of the second and third FETs. The first and second current source circuits respectively include first and second current source FETs having the first and second drive voltages as gate voltages, and a start-up circuit changing the first and second drive voltages forcedly when the first and second current source FETs are made conductive.Type: GrantFiled: July 18, 2008Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Nobukazu Murata
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Publication number: 20110205815Abstract: The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.Type: ApplicationFiled: February 22, 2011Publication date: August 25, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Nobukazu Murata