Abstract: Each of a plurality of first radio units are installed in a plurality of first cells making up a first area, each of a plurality of second radio units are installed in a plurality of second cells making up a second area being separated from the first area, a first radio control unit is constantly connected to a plurality of the first radio units that serve about half of traffic peak in the first area and constantly connected to a plurality of the second radio units that serve about half of traffic peak in the second area, a second radio control unit is constantly connected to the remaining plurality of the first radio units and constantly connected to the remaining plurality of the second radio units, and an upper controller is connected to the first radio control unit and the second radio control unit.

Abstract: Each of a plurality of first radio units are installed in a plurality of first cells making up a first area, each of a plurality of second radio units are installed in a plurality of second cells making up a second area being separated from the first area, a first radio control unit is constantly connected to a plurality of the first radio units that serve about half of traffic peak in the first area and constantly connected to a plurality of the second radio units that serve about half of traffic peak in the second area, a second radio control unit is constantly connected to the remaining plurality of the first radio units and constantly connected to the remaining plurality of the second radio units, and an upper controller is connected to the first radio control unit and the second radio control unit.

Abstract: This multiprocessor circuit has interruption restriction circuits connected between the interruption line, which is provided for inputting interruption signals, and each of the CPUs connected in parallel. The interruption restriction circuits restrict the input of interruption signals to each CPU under certain conditions. Each interruption restriction circuit counts the number of interruption signals received by each corresponding CPU during a specified period set at the timer, using a counter. When the count for a CPU exceeds the predetermined value, the multiprocessor circuit causes the input disabling means to disable the input of interruption signals to that CPU for a certain period of time and thereby distributes the interruption signals to a plurality of CPUs more equally.