Abstract: A fishing reel cap for mounting on a reel body of a fishing reel includes a bottomed cylindrical cap body and an annular reinforcing member. The bottomed cylindrical cap body has a cylindrical portion with threads capable of being screwed onto threads on the reel body and projections extending radially outward on an outside surface of the cylindrical portion. The annular reinforcing member has recesses, a portion of each projection of the projections being configured to fit into a respective recess of the recesses, and the annular reinforcing member being configured to fit on the outside surface of the cap body, exposing at least a portion of each of the projections in a radially outward direction.

Abstract: A fishing reel cap for mounting on a reel body of a fishing reel includes a bottomed cylindrical cap body and an annular reinforcing member. The bottomed cylindrical cap body has a cylindrical portion with threads capable of being screwed onto threads on the reel body and projections extending radially outward on an outside surface of the cylindrical portion. The annular reinforcing member has recesses, a portion of each projection of the projections being configured to fit into a respective recess of the recesses, and the annular reinforcing member being configured to fit on the outside surface of the cap body, exposing at least a portion of each of the projections in a radially outward direction.

Abstract: A semiconductor integrated circuit device includes a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register. The first flip-flop of the plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes the first output signal based on the first selection control signal. A second flip-flop of the plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes the second output signal based on a second selection control signal. The semiconductor integrated circuit device further includes a control circuit configured to generate the first and second selection control signals such that a period during which the first flip-flop fixes the first output signal is different from a period during which the second flip-flop fixes the second output signal.

Abstract: A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to other hard macros of the plurality of hard macros in order.

Abstract: A semiconductor integrated circuit device includes a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register. The first flip-flop of the plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes the first output signal based on the first selection control signal. A second flip-flop of the plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes the second output signal based on a second selection control signal. The semiconductor integrated circuit device further includes a control circuit configured to generate the first and second selection control signals such that a period during which the first flip-flop fixes the first output signal is different from a period during which the second flip-flop fixes the second output signal.

Abstract: The present invention provides a metal coated fiber with excellent coating strength and corrosion resistance, and a conductive resin composition with excellent conductivity. A feature of a metal coated fiber of the present invention is that following provision of a metal coating on the surface of the fiber, heat treatment is conducted at a temperature greater than the crystallization temperature but less than the melting temperature of the fiber. Gradual cooling is preferably performed following the heat treatment. Furthermore, a conductive metal coating may be provided as the metal coating, and an additional corrosion resistant metal coating then laminated onto the surface of the conductive metal coating. In addition, a feature of a conductive resin composition of the present invention is that metal coated short fibers, formed by providing a conductive metal coating on the surface of a substrate fiber formed from a synthetic resin and then conducting heat treatment, are mixed into a substrate resin.

Abstract: A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to other hard macros of the plurality of hard macros in order.

Abstract: The present invention provides a metal coated fiber with excellent coating strength and corrosion resistance, and a conductive resin composition with excellent conductivity. A feature of a metal coated fiber of the present invention is that following provision of a metal coating on the surface of the fiber, heat treatment is conducted at a temperature greater than the crystallization temperature but less than the melting temperature of the fiber. Gradual cooling is preferably performed following the heat treatment. Furthermore, a conductive metal coating may be provided as the metal coating, and an additional corrosion resistant metal coating then laminated onto the surface of the conductive metal coating. In addition, a feature of a conductive resin composition of the present invention is that metal coated short fibers, formed by providing a conductive metal coating on the surface of a substrate fiber formed from a synthetic resin and then conducting heat treatment, are mixed into a substrate resin.

Abstract: A white conductive fiber is manufactured at an inexpensive cost having superior conductivity and high degree of whiteness, in which a metal coating plated on the fiber has superior adhesiveness. A method for manufacturing the white conductive fiber comprises the steps of mounting a wound fiber body formed by winding a continuous fiber to the fixing shaft, a step of flowing a plating solution from the fixing shaft to a plating bath via the wound fiber body so as to infiltrate the plating solution into the wound fiber body, and a step of performing electroless plating of silver, platinum, or the like on the fiber material while the plating solution flows.

Abstract: A control system for transmission devices equipped with a high-efficiency coding scheme in a communication network which avoids degradation of the quality of an acoustic signal for transmission and permits an efficient transfer of the acoustic signal. The control system has a structure in which: information on a high-efficiency coding scheme used in the preceding transmission device is sent to the current exchange from the preceding one through the use of an out-band signaling system for transmitting and receiving a call control signal via a channel different from a speech channel; and based on the information sent to the current exchange, second-placed transmission devices connected to the current and following exchanges avoid effectively decoding/coding of the acoustic signal transferred thereto, or the use of these transmission devices is avoided.

Abstract: A semiconductor memory device comprises a word lines (15), pairs of complementary data lines (17, 18), memory elements (MC11) respectively arranged at each intersection of the word lines and the pairs of complementary data lines, pairs of complementary signal lines (17s, 18s) each associated with a sense amplifiers (SA) and selectively connected to one of the pairs of complementary data lines via a pair of transfer gate transistors (7, 8), first precharge means (5, 6) for charging the pairs of complementary data lines and second precharge means (19, 20) for charging the pairs of complementary signal lines. The second precharge means charge the pairs of complementary signal lines to a first voltage (V.sub.D), the first precharge means charge the pairs of complementary signal lines to a second voltage (V.sub.D -V.sub.t) which is smaller than the first voltage by a threshold voltage (V.sub.

Abstract: An addressing system comprises an address buffer unit responsive to a clock signal of a low level for latching an address signal indicative of one of word lines, and maintaining the address signal until the clock signal is shifted to from a high level to the low level again; an address decoder unit coupled with the address buffer unit for selectively driving decoded signal lines; a timing control unit responsive to the clock signal for producing an in-phase timing signal; and a driver unit having a plurality of driver circuits respectively coupled between the decoded signal lines and the plurality of word lines, wherein the plurality of driver circuits are operative to respectively latch logic levels on the associated decoded signal lines when the in-phase timing signal is shifted from the low level to the high level so as to selectively drive the address lines to active level, and maintains all of the word lines in inactive level while the in-phase timing signal remains in the low level, thereby preventing t