Patents by Inventor Nobuo Iwase
Nobuo Iwase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6068872Abstract: The vacuum-heat processing apparatus according to the present invention includes: a vacuum container forming a vacuum chamber; a hopper into which an object to be processed and a processing liquid adjusted to a first temperature are thrown, the hopper being arranged above and communicating with an intake port formed in an upper end portion of the vacuum container; a sealing member arranged between the hopper and the intake port of the vacuum container to keep the vacuum chamber airtight; a transport conveyor installed in the vacuum chamber below the intake port to receive at one end side thereof the object flowing down the hopper from the intake port through the sealing member and carry it to the other end side; a processing liquid showering nozzles installed in the vacuum chamber immediately above the transport conveyor to shower a processing liquid adjusted to a second temperature over the object on the transport conveyor; a processing liquid tank containing a processing liquid adjusted to a third temperatuType: GrantFiled: October 5, 1999Date of Patent: May 30, 2000Assignees: Asahi Engineering Co., Ltd., Iwase Corporation Ltd.Inventors: Toshio Hashiguchi, Nobuo Myojin, Nobuo Iwase, Tetsuya Hayashi
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Patent number: 5988051Abstract: The vacuum-heat processing apparatus according to the present invention includes: a vacuum container forming a vacuum chamber; a hopper into which an object to be processed and a processing liquid adjusted to a first temperature are thrown, the hopper being arranged above and communicating with an intake port formed in an upper end portion of the vacuum container; a sealing member arranged between the hopper and the intake port of the vacuum container to keep the vacuum chamber airtight; a transport conveyor installed in the vacuum chamber below the intake port to receive at one end side thereof the object flowing down the hopper from the intake port through the sealing member and carry it to the other end side; a processing liquid showering nozzles installed in the vacuum chamber immediately above the transport conveyor to shower a processing liquid adjusted to a second temperature over the object on the transport conveyor; and a processing liquid tank containing a processing liquid adjusted to a third tempeType: GrantFiled: June 29, 1998Date of Patent: November 23, 1999Assignee: Asahi Engineering Co., Ltd.Inventors: Toshio Hashiguchi, Nobuo Myojin, Nobuo Iwase, Tetsuya Hayashi
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Patent number: 5909058Abstract: A thin type semiconductor package having a low thermal resistance and a low electric resistance is disclosed, that comprises a nitride ceramic supporting substrate having a first main surface and a second main surface, the nitride ceramic supporting substrate having via-holes that pass through from the first main surface to the second main surface, a resin film having a wiring layer, the resin film being bonded to the first main surface of the supporting substrate, the wiring layer being electrically connected to an edge portion of the via-holes on the first main surface, the resin film having an opening region, a semiconductor chip directly mounted on the first main surface of the nitride ceramic supporting substrate, disposed at the opening region of the resin film, and electrically connected to the wiring layer of the resin film, and external connection terminals disposed on the edge portion of the via-holes of the second main surface.Type: GrantFiled: September 22, 1997Date of Patent: June 1, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Keiichi Yano, Hironori Asai, Kaoru Koiwa, Nobuo Iwase
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Patent number: 5907187Abstract: In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.Type: GrantFiled: July 14, 1995Date of Patent: May 25, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kaoru Koiwa, Koji Yamakawa, Kiyoshi Iyogi, Takaaki Yasumoto, Nobuo Iwase
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Patent number: 5622769Abstract: According to this invention, there is disclosed a thermal conductivity substrate which includes an aluminum nitride sintered body and a coating layer formed on the body of aluminum phosphate and having a surface roughness of 1 .mu.m or less, and which has excellent humidity resistance and chemical resistance.Type: GrantFiled: February 10, 1994Date of Patent: April 22, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Kozuka, Masaru Hayashi, Katsuyoshi Oh-Ishi, Takaaki Yasumoto, Nobuo Iwase, Hiroshi Endo, Koji Yamakawa, Kaoru Koiwa, Kiyoshi Iyogi
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Patent number: 5453991Abstract: A highly-integrated semiconductor IC device includes a semiconductive substrate, on which an internal function circuit is arranged to have a first plurality of input terminals and a second plurality of output terminals. A logic circuit is arranged on the substrate and is connected to the internal circuit through the output terminals. The logic circuit has a third plurality of output terminals, which are less in number than the outputs of the internal circuit. These logic output terminals are coupled to the same number of inspection terminals, which are adapted to be coupled to a known electric inspection tool. The logic circuit processes the voltage signals appearing at the output terminals of the internal circuit so as to cause these signals to decrease in number. The output signals of the logic circuit are sent to the inspection terminals as monitor signals, based on which an inspection is carried out to determine whether the internal circuit operates normally.Type: GrantFiled: March 15, 1993Date of Patent: September 26, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Kouhei Suzuki, Kouji Suzuki, Miki Mori, Akinori Hongu, Nobuo Iwase
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Patent number: 5412160Abstract: A circuit board comprising a substrate, at least one dielectric film formed on the substrate and made of at least one selected from the group consisting of AlN, BN, diamond, diamond-like carbon, BeO and SiC, the dielectric film having pores of a porosity of 5 to 95% by volume, and at least one wiring metal film formed on the dielectric film.Type: GrantFiled: March 15, 1994Date of Patent: May 2, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takaaki Yasumoto, Nobuo Iwase, Kaoru Koiwa, Koji Yamakawa, Kiyoshi Iyogi
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Patent number: 5326623Abstract: A circuit board including a circuit pattern adhered firmly to a ceramic substrate and capable of eliminating an increase in resistivity due to an influence of an external environment, particularly, a thermal influence is disclosed. The circuit board comprises a ceramic substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a bonding layer comprising Ti and at least one element selected from the group consisting of N and O, a conductor layer consisting essentially of Cu, and a protective layer comprising Ti and at least one element selected from the group consisting of N and O are stacked in the order named.Type: GrantFiled: January 28, 1993Date of Patent: July 5, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Kaoru Koiwa, Takaaki Yasumoto, Kiyoshi Iyogi, Nobuo Iwase
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Patent number: 5041700Abstract: A circuit board includes an aluminum nitride substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a metal oxynitride layer represented by formula Al.sub.u Ml.sub.v M2.sub.x O.sub.y N.sub.z (wherein M1 represents a metal selected from the group consisting of Ti, Cr, Ta, and Zr, M2 represents a metal selected from the group consisting of Ni, Pt, Pd, W, Nb, and Mo, u represents 3 to 50 atm %, v represents 3 to 78 atm %, x represents 0 to 50 atm %, y represents 0.005 to 25 atm %, and z represents 5 to 70 atm %), a bonding layer consisting essentially of a metal represented by M1, a barrier layer consisting essentially of a metal represented by M2, and a conductor layer consisting essentially of Au are stacked in the order named.Type: GrantFiled: September 27, 1990Date of Patent: August 20, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Takaaki Yasumoto, Toshirou Yanazawa, Nobuo Iwase
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Patent number: 5008582Abstract: In an electric device having a package included an electric circuit element therein, a cooling fan is fixed on the package directly. The fan is formed of piezoelectric elements and a flexible cooling fin. The fan generates the cooling air flow due to vibration of the piezoelectric elements.Type: GrantFiled: April 26, 1990Date of Patent: April 16, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Chiaki Tanuma, Kazuhiro Itsumi, Nobuo Iwase, Tomio Ono, Yuu Kondo, Kazutaka Saito
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Patent number: 4970571Abstract: According to the present invention, there is provided a method for forming a bump and comprising the steps of dipping a semiconductor element with an Al electrode and a passivation film formed thereon in a palladium solution containing 5 to 2,000 ppm of at least one element selected from the group consisting of Zn, Pb, Sn, Cd, and Cr, selectively precipitating palladium on the electrode, and conducting electroless nickel-plating on the semiconductor element, including the electrode on which palladium is precipitated.Type: GrantFiled: September 23, 1988Date of Patent: November 13, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Nobuo Iwase, Michihiko Inaba
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Patent number: 4963701Abstract: Disclosed is an aluminum nitride thin film circuit board having an aluminum nitride substrate and a conductive thin film pattern formed on the substrate. The conductive thin film pattern has a multi-layer structure selected from the group consisting of Ti/Ni/Au, Ti/Pd/Au, Ti/Pt/Au, Ni/Au, Cr/Au, and Cr/Cu/Au, and a boundary layer of Al-N-M-O (M is Ti, Ni, or Cr) is formed between the substrate and the conductive thin film pattern. Since the boundary layer is formed, bonding properties between the substrate and the conductive thin film pattern are improved. In particular, when the boundary layer contains 0.02 to 30 atomic % of oxygen, a higher bonding strength can be obtained.Type: GrantFiled: January 24, 1989Date of Patent: October 16, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Takaaki Yasumoto, Nobuo Iwase
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Patent number: 4919731Abstract: The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements.Type: GrantFiled: February 10, 1989Date of Patent: April 24, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Takaaki Yasumoto, Toshirou Yanazawa, Nobuo Iwase, Masako Nakahashi, Hiromitsu Takeda
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Patent number: 4916261Abstract: A circuit substrate comprises a sintered oxide body of barium, tin and boron as an insulating body which is able to be fired at a temperature less than 1300.degree. C. The circuit substrate is further improved in moisture resistance by containing titanium or securing substantially the composition of BaSn(BO.sub.3).sub.2.Type: GrantFiled: September 7, 1984Date of Patent: April 10, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Truong D. Thanh, Nobuo Iwase
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Patent number: 4906341Abstract: A plating solution is stored in an annular plating solution storage. A plating solution tank having an open upper portion is arranged in a hollow portion of the storage. A mesh-like anode electrode is arranged on the bottom portion of the plating tank. Hold members are attached to an upper side wall of the plating tank. One of the hold members is in contact with a portion to be plated of a semiconductor member and serves as a cathode electrode. The anode and cathode electrodes are connected to a DC power source. The plating solution in the plating solution tank is brought into contact with the portion to be plated and is isolated therefrom by an driving pump intermittently driven at predetermined intervals using an intermittent drive unit. The power source is kept in the ON state while the plating solution is in contact with the portion to be plated, there-by forming a plated layer on the portion to be plated.Type: GrantFiled: September 22, 1988Date of Patent: March 6, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Kaoru Koiwa, Nobuo Iwase
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Patent number: 4855251Abstract: According to the present invention, a method is provided of manufacturing electronic parts, comprising a first step of forming on the surface of a substrate a bump wherein the metal particles of that portion of the bump which contacts the surface of the substrate have a larger diameter than the metal particles of that portion of the bump which does not contact the surface of the substrate, a second step of transferring the bump to an electrode lead, and a third step of connecting an electrode lead to a predetermined electrode section of the semiconductor chip, by means of the transferred bump. The method of the present invention ensures that the bump does not fall off during the electroplating and washing steps, and ensures a high-strength bond between the transferred bump and the electrode section of a semiconductor chip.Type: GrantFiled: November 3, 1988Date of Patent: August 8, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Koji Yamakawa, Nobuo Iwase
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Patent number: 4835344Abstract: The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements.Type: GrantFiled: February 10, 1988Date of Patent: May 30, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Iyogi, Takaaki Yasumoto, Toshirou Yanazawa, Nobuo Iwase, Masako Nakahashi, Hiromitsu Takeda
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Patent number: 4797530Abstract: A ceramic circuit substrate can be manufactured by a method comprising the steps of (i) providing an electrically insulating ceramic substrate; and (ii) irradiating a predetermined region of said ceramic substrate with an energy beam such that at least a portion of said region is rendered conductive.Type: GrantFiled: December 10, 1986Date of Patent: January 10, 1989Assignee: Kabushiki Kaisha ToshibaInventor: Nobuo Iwase
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Patent number: 4772985Abstract: Disclosed is a thick film capacitor comprising (a) a sintered layer of a ferroelectric material mainly consisting of one or more ferroelectric inorganic compounds having a perovskite structure and an inorganic binder having a eutectic composition which experiences a liquid phase at a temperature lower than the sintering temperature of the ferroelectric inorganic compounds, and (b) at least two electrodes formed on both surfaces of the sintered layer of the ferroelectric material. In the thick film capacitor of this invention, the perovskite structure of the ferroelectric inorganic compounds is not destroyed upon sintering. Therefore, a high degree of sintering, a good dielectric characteristic and high moisture and migration resistances can be obtained.Type: GrantFiled: September 18, 1987Date of Patent: September 20, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Takaaki Yasumoto, Osamu Furukawa, Nobuo Iwase, Mitsuo Harata, Masao Segawa
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Patent number: 4659611Abstract: A high thermal conductivity circuit substrate is provided comprising a sintered aluminum nitride ceramic substrate consisting essentially of one member selected from the group of yttrium, the rare earth metals and the alkali earth metals and an electrically conductive thick film paste for a conductive layer formed on the substrate.Type: GrantFiled: February 27, 1985Date of Patent: April 21, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Iwase, Kazuo Anzai, Kazuo Shinozaki, Akihiko Tsuge, Kazutaka Saitoh, Kiyoshi Iyogi, Noboru Sato, Mitsuo Kasori