Abstract: An optical imaging system with a flexible cable having a first end and a second end. The cable has a central core element including a flexible optical conduit, with a number of wires surrounding the core element to form a tube concentric with an axis defined by the center of the core. The cable has a conductive shield layer surrounding the wires and uniformly spaced apart from the wires An electronic instrument is connected to the first end of the cable and has an illuminator coupled with the optical conduit and a display device connected to the wires. An image transducer is connected to the second end of the cable and is connected to the wires. The wires may be twisted pairs evenly spaced apart from each other, and evenly spaced apart from an axis defined by the core.

Abstract: A spherical semiconductor device includes a spherical semiconductor element having one or more electrodes on its surface. Spherical conductive bumps are formed at the positions of the electrodes. The electrodes are so arranged as to contact a common plane. Spherical bumps constituting a group to be connected to the outside protrude above the spherical semiconductor element such that a predetermined gap is formed between a plane or a spherical surface capable of contacting the spherical bumps and the surface of the spherical semiconductor element. The spherical semiconductor device is connected to various circuit boards or another semiconductor device through the spherical bumps. This affords easy and accurate electrical connections to the outside.

Abstract: A spherical semiconductor device includes a spherical semiconductor element having one or more electrodes on its surface. Spherical conductive bumps are formed at the positions of the electrodes. The electrodes are so arranged as to contact a common plane. Spherical bumps constituting a group to be connected to the outside protrude above the spherical semiconductor element such that a predetermined gap is formed between a plane or a spherical surface capable of contacting the spherical bumps and the surface of the spherical semiconductor element. The spherical semiconductor device is connected to various circuit boards or another semiconductor device through the spherical bumps. This affords easy and accurate electrical connections to the outside.

Abstract: A spherical semiconductor device includes a spherical semiconductor element having one or more electrodes on its surface. Spherical conductive bumps are formed at the positions of the electrodes. The electrodes are so arranged as to contact a common plane. Spherical bumps constituting a group to be connected to the outside protrude above the spherical semiconductor element such that a predetermined gap is formed between a plane or a spherical surface capable of contacting the spherical bumps and the surface of the spherical semiconductor element. The spherical semiconductor device is connected to various circuit boards or another semiconductor device through the spherical bumps. This affords easy and accurate electrical connections to the outside.

Abstract: A system and method for forming solder bumps on a surface of a semiconductor device, such as a spherical-shaped semiconductor integrated circuit, is disclosed. Multiple devices are first aligned so that a vacuum chuck can hold all of the devices with an appropriate orientation. The vacuum chuck can then dip the devices into different molten metal compounds to form a plurality of solder bumps. Metal solder materials of different melting points are chosen so that the thickness of the solder bumps are partially controlled by the number of layers of solder metal sequentially grow on the metal pads. Once the solder bumps are grown on the devices, the vacuum chuck can immediately transfer the devices to a tape and reel assembly for further transportation thereof. It can also be easily fed into a tube assembly which protects the spherical shaped semiconductor device with the solder bumps during the shipping process.

Abstract: A system and a method for focusing an image onto the surface of a nonplanar substrate or device, such as a spherical semiconductor substrate, that substantially eliminates misalignment and overlapping problems between neighboring images. The system includes a plurality of mirrors arranged in a ring, a support reciprocatingly positioned relative to the center of the ring of mirrors for positioning the nonplanar substrate or device relative to the ring of mirrors. The nonplanar substrate or device is positioned such that each mirror will be capable of reflecting a focused image onto the surface of the substrate. The image is generated using a mask positioned relative to the ring of mirrors and illuminated to project the image onto the surface of the nonplanar substrate or device.

Abstract: A method for designing a circuit on a spherical shaped semiconductor integrated circuit using uniform unit shapes capable of cover the surface of the sphere in a matingly corresponding orientation with adjacent unit shapes. The method includes the steps of designing a circuit within each unit shape selected from various types of unit shape patterns; selecting a predetermined number of those unit shapes from the various types of unit shape patterns; and covering the spherical integrated circuit with the predetermined number of unit shapes. Furthermore, the designer can use the unit shapes to navigate over the surface to accurately determine the location, the position, and surface area remaining.

Abstract: A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

Abstract: A tungsten film is formed in two steps in a tungsten chemical vapor deposition method of the present invention. In a first step, a first thin tungsten film is selectively grown on a surface of a silicon substrate by a silicon reduction using a WF.sub.6 gas as a tungsten source, followed by a second step in which another tungsten film is formed on the first tungsten film by a silane reduction using a WF.sub.6 gas as a tungsten source. The state of the silicon substrate surface is monitored by a pyrometer, and the timing of change from the silicon reduction to the silane reduction is determined on the basis of the intensity of the infrared ray radiation.

Abstract: This invention provides a step cut type insulated gate static induction tsistor having a first main electrode formed in one major surface of a semiconductor substrate, a second main electrode formed in a bottom portion of a U-shaped groove formed in one major surface of a semiconductor substrate, a control electrode formed on a side wall of the U-shaped groove and consisting of a thin insulating film and a polysilicon layer, and a low-resistance electrode of a refractory metal layer or a refractory metal silicide layer formed in at least part of the side wall of the polysilicon layer of the control electrode.

Abstract: A step-cut insulated gate static induction transistor can accurately make a channel length and a gate length and is excellent as a high speed transistor but is greatly affected by a deviation in mask alignment in the manufacturing process. This invention utilizes the fact that a gate portion formed in a previous processes is used as a mask in a post portion to thereby self-adjustably form the post portion, thus eliminating the influence of the deviation in mask alignment. In addition, a construction has been invented in which a current flowing through a portion apart from a gate between a drain and a source can be restricted. The aforesaid manufacturing method is also used for this improved construction.

Abstract: This invention provides a step cut type insulated gate static induction tsistor having a first main electrode formed in one major surface of a semiconductor substrate, a second main electrode formed in a bottom portion of a U-shaped groove formed in one major surface of a semiconductor substrate, a control electrode formed on a side wall of the U-shaped groove and consisting of a thin insulating film and a polysilicon layer, and a low-resistance electrode of a refractory metal layer or a refractory metal silicide layer formed in at least part of the side wall of the polysilicon layer of the control electrode.

Abstract: A hetero-junction static induction transistor (SIT) of normal or upside-down type to be operated by applying a forward bias across the gate and source regions, in which at least its source region and gate region among the source, drain and gate regions is formed with a material having a band gap broader than that of the channel region. Such a SIT provides a large current amplification factor, improved frequency characteristics and is suitable for high power operation and for use in semiconductor integrated circuits.