Abstract: To achieve a reduction in waste heat loss of a fuel with improved efficiency in arrangement of a plurality of cavities, or manifold spaces. A multi-stage combustor includes a combustor liner configured to define a combustion chamber therein, a plurality of fuel nozzles configured to inject a fuel, and a manifold configured to distribute the fuel to the plurality of fuel nozzles. The manifold is disposed on a central axis of the combustor liner in a central axis extending direction. The manifold includes a casing and a plurality of partitions inserted in the casing so as to be arranged in a central axis direction of the combustor liner to define a plurality of cavities divided by the partitions. The plurality of cavities are layered in the central axis direction of the combustor liner inside of the casing, and are connected to the corresponding fuel nozzles.

Abstract: To achieve a reduction in waste heat loss of a fuel with improved efficiency in arrangement of a plurality of cavities, or manifold spaces. A multi-stage combustor includes a combustor liner configured to define a combustion chamber therein, a plurality of fuel nozzles configured to inject a fuel, and a manifold configured to distribute the fuel to the plurality of fuel nozzles. The manifold is disposed on a central axis of the combustor liner in a central axis extending direction. The manifold includes a casing and a plurality of partitions inserted in the casing so as to be arranged in a central axis direction of the combustor liner to define a plurality of cavities divided by the partitions. The plurality of cavities are layered in the central axis direction of the combustor liner inside of the casing, and are connected to the corresponding fuel nozzles.

Abstract: In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.

Abstract: A system having an SMP connection made among each information processing apparatus in units of a module including a CPU, a main memory, an HDD and the like, allows use of the HDDs distributed in the system as a single disk. The SMP connection is made among information processing apparatuses each including one or more CPUs, a main memory, one or more storage devices, and a storage device controller that controls the storage device. The storage device controller in a certain information processing apparatus controls the storage device in the information processing apparatus and the storage device in another information processing apparatus. Each information processing apparatus includes a storage device switch for exclusively switching which of the storage device controller in the information processing apparatus and the storage device controller in another information processing apparatus is connected to the storage device in the information processing apparatus.

Abstract: A gas turbine combustor comprising a burner including: a plurality of fuel nozzles to supply a fuel; a fuel nozzle plate to supports end portions of the fuel nozzles structurally and being configured to distribute the fuel flowing from an upstream side to the fuel nozzles; and a swirler including a plurality of air holes to supply combustion air, characterized in that the fuel nozzle plate is provided with a fuel nozzle receiving hole to receive the fuel nozzle, and the fuel nozzle plate and the fuel nozzle inserted in the fuel nozzle receiving hole are connected to each other from an upstream side of the fuel nozzle plate by welding.

Abstract: In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.

Abstract: A system having an SMP connection made among each information processing apparatus in units of a module including a CPU, a main memory, an HDD and the like, allows use of the HDDs distributed in the system as a single disk. The SMP connection is made among information processing apparatuses each including one or more CPUs, a main memory, one or more storage devices, and a storage device controller that controls the storage device. The storage device controller in a certain information processing apparatus controls the storage device in the information processing apparatus and the storage device in another information processing apparatus. Each information processing apparatus includes a storage device switch for exclusively switching which of the storage device controller in the information processing apparatus and the storage device controller in another information processing apparatus is connected to the storage device in the information processing apparatus.

Abstract: A root port connection functioning as a PCI express bridge, and having a PCI express path constituting a PCI express tree having a PCI express device or switch; when detecting a failure on a PCI express path, a PCI express device or switch transmits a failure signal; the root port transmits an SMI responsive to the failure signal; the CPU executes the BIOS responsive to the SMI; the BIOS collects a log of the PCI express path where failure is detected, analyzes the collected log to judge failure type, and upon a fatal failure on the PCI express path, resets the PCI express tree downstream of the root port that received the failure signal, and upon a non-fatal failure on the PCI express path, resets the PCI express device in which the failure occurred; and the CPU closes the reset PCI express device by executing the device driver.

Abstract: A root port connection functioning as a PCI express bridge, and having a PCI express path constituting a PCI express tree having a PCI express device or switch; when detecting a failure on a PCI express path, a PCI express device or switch transmits a failure signal; the root port transmits an SMI responsive to the failure signal; the CPU executes the BIOS responsive to the SMI; the BIOS collects a log of the PCI express path where failure is detected, analyzes the collected log to judge failure type, and upon a fatal failure on the PCI express path, resets the PCI express tree downstream of the root port that received the failure signal, and upon a non-fatal failure on the PCI express path, resets the PCI express device in which the failure occurred; and the CPU closes the reset PCI express device by executing the device driver.

Abstract: A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred.

Abstract: It is desirable to flexibly provide a single information processing device with a system capable of connecting a large number of input-output devices, and an inexpensive system capable of sharing an input-output device by a plurality of servers. To achieve this, there is provided an information system including a server chassis and an IO chassis. The server chassis includes a plurality of server blades each having a processor, a memory, and a root complex, and a first multi-root PCIe switch connected to the individual server blades. The IO chassis includes a plurality of PCIe slots to which input-output devices are attached, and a second multi-root PCIe switch connected to the individual PCIe slots. The first multi-root PCIe switch and the second multi-root PCIe switch are connected together by a PCIe cable.

Abstract: A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred.

Abstract: A system controller which controls a plurality of storage devices comprises a unit which divides data of processor bus width from a processor into a plurality of divided data, a first transfer unit which simultaneously transfers the divided plurality of divided data to the plurality of storage devices distributing them, a second transfer unit which time divides the divided plurality of divided data and sequentially transfers them to the same storage device, and a mode control unit which operates either the first transfer unit or the second transfer unit.

Abstract: Destination registers are provided in a chipset and node information is set in the destination registers. The destination address is selected in accordance with a physical address to be accessed to thereby decided a node provided with a memory to be accessed. The magnitude of the load of the memory access to the node can be changed in accordance with setting of the node information in the destination registers. Optimum node information can be set in the destination registers in accordance with the number of nodes increased and the transfer speed and the capacity of the memory to thereby increase the flexibility and uniform the throughput of memory access to each node.

Abstract: An information processing apparatus includes a data ownership table which is a list of processor numbers having data on each of lines in a level 2 cache. When data at an address pointed by a store instruction exists in the level 2 cache, the apparatus references the table to selectively issue an invalidation request only to a processor in which data at the address exists, but does not issue the request to a processor in which the data does not exist. The path busy ratio can be reduced and the data coherency among processors and a system controller can be maintained with a small amount of logics. When a system controller is divided into a plurality of interleaves operating independently of one another and respectively issuing an invalidation request, the requests issued from the interleaves are put into a queue, and requests having different destination processor numbers are simultaneously issued.

Abstract: A method for preparing a molded product which includes (i) molding a fiber-reinforced plastic material in a mold, (ii) injecting a coating composition into the mold, the coating composition containing a vehicle component including urethane acrylate oligomer and epoxy acrylate oligomer as the main ingredients and a filler component including calcium carbonate as the main ingredient, and (iii) taking the coated molded product from the mold and plating the surface of the product. According to the present invention, there can be obtained a molded product having a plated layer with a satisfactory smooth and uniform glossy surface and having an improved adhesion between the molded product and the plated layer.

Abstract: An industrial robot apparatus comprise for controlling an industrial robot and a peripheral unit thereof according to a program so as to load workpieces on a pallet, an abnormal stop unit for detecting an abnormality which occurs in at least either of the industrial robot and the peripheral unit and for stopping both the industrial robot and the peripheral unit, a storage unit for storing a step of the program which is being executed when the abnormal stop takes place, and a removal unit for removing remaining workpieces to be loaded on the pallet in steps following the stored step of the storage unit.