Abstract: Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.

Abstract: Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.

Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

Abstract: A semiconductor device and a method of controlling the semiconductor device, the semiconductor device including: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal including: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is included of the entire remaining portion of the address data not including the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address data to the other one of the first in

Abstract: The present invention provides a semiconductor device and a method of controlling the semiconductor device, the semiconductor device comprising: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal comprising: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is comprised of the entire remaining portion of the address data not comprising the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address da

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.

Abstract: A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

Abstract: A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells each holding memory cell information are arrayed, reference cells which supply different reference currents respectively, and a read-out circuit. When reading the memory cell information from a selected one of the memory cells, the read-out circuit is brought into conduction to a first global bit line which is connected to a bit line of the selected memory cell, and brought into conduction to one of a plurality of second global bit lines respectively which are provided near the first global bit line and connected to bit lines of non-selected memory cells but not connected to the bit line of the selected memory cell, so that the memory cell information is determined by comparing a read-out current from the selected memory cell with each of the reference currents from the reference cells.

Abstract: A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.

Abstract: A semiconductor device comprising a dummy interface circuit approximating to an external interface circuit with high accuracy is disclosed. The device further comprises a dummy interface circuit for internally generating, by simulation, a dummy output signal equivalent to the level of the output signal of the external interface circuit. The dummy interface circuit includes a dummy signal output circuit for producing a dummy output signal at a dummy output line, a dummy capacitor connected to the dummy output line, and a dummy load circuit connected to the dummy output line for converting the dummy output signal into a signal of a level corresponding to the output signal level of the external interface.

Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.

Abstract: A variable delay circuit generates a controlling clock signal by delaying a reference clock signal by a predetermined time. A dummy circuit delays the controlling clock signal by a predetermined time to generate a delayed clock signal. A phase comparator compares the delayed clock signal and the reference clock signal in phase. A delay control circuit adjusts the delay time of the variable delay circuit in accordance with a plurality of phase comparison results from the phase comparator, to have the delayed clock signal coincide with the reference clock signal in phase. Performing a single phase adjustment corresponding to a plurality of phase comparison results, prevents a delay in feeding back the controlling clock signal (delayed clock signal) transmitted through the dummy circuit to the phase comparator. This avoids extra operations of the delay control circuit and the variable delay circuit. Thus, jitter in the controlling clock signal is reduced.

Abstract: A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

Abstract: A delay time adjusting circuit adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The circuit comprises first dividing means for dividing a frequency of the input signal by a first frequency division rate; delaying means for delaying the input signal by a predetermined time; second dividing means for dividing a frequency of the input signal delayed by the delaying means by a second frequency division rate; comparing means for comparing a phase of a signal generated by the first dividing means and a phase of a signal generated by the second dividing means; and adjusting means for adjusting the predetermined time according to a comparison result obtained by the comparing means.

Abstract: The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase adjustment by smaller, fine delay unit. When phase adjustment begins, only the rough DLL circuit operates; when the rough DLL circuit locks on, phase adjustment by the rough DLL circuit ends and the delay amount of the rough DLL circuit is set. When the rough DLL circuit locks on, the fine DLL circuit is caused to operate. In this way, the phase of the timing clock generated by the DLL circuit is adjusted only by fine delay units even if the phase of the reference clock is temporarily shifted by a large amount due to power source noise or the like. Consequently, in the event of temporary phase shifting, the amount of jitter in the timing clock can be suppressed to the small amount of a fine delay unit.