Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

Abstract: A semiconductor memory device according to an embodiment may include a plurality of memory cells arranged on a semiconductor substrate includes a tunneling dielectric film on the semiconductor substrate; a floating gate formed on the tunneling dielectric film and corresponding to each of the memory cells; an inter-gate dielectric film on the floating gate; and a control gate on the inter-gate dielectric film, wherein the floating gate corresponding to a single memory cell has a first gate part, a second gate part, and the floating gate has a part that the tunneling dielectric film contacts the inter-gate dielectric film is provided between the first gate part and the second gate part within the memory cell.

Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.

Abstract: A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.

Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.

Abstract: A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

Abstract: A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

Abstract: A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

Abstract: A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1.

Abstract: It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

Abstract: It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.

Abstract: In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor.

Abstract: In one aspect of the present invention, A semiconductor device, may include a transistor including a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a gate stacked above the semiconductor substrate with the insulating film placed in between, and element isolation trenches formed in the semiconductor substrate to define an element formation region in which the transistor is to be formed, wherein the semiconductor substrate includes a narrow portion therein, the narrow portion formed by partially narrowing down the element formation region from the side surfaces of the element isolation trenches in the gate width directions in the substrate.

Abstract: A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.