Abstract: An electrical device, in which can easily detect an operation status just before a stoppage of a power supply or an error occurrence when a system is returned, even if the power supply is cut off or the error occurs during executing program or erase operation, is provided. The electric device with a flash memory built-in including an auxiliary non-volatile memory for recording bus information for connecting the flash memory and a control section for controlling the flash memory. The auxiliary non-volatile memory is preferably to a memory, in which data write operation can be executed higher than the flash memory, for example, a ferroelectric RAM (FeRAM). The FeRAM, which is a memory using a polarization of ferroelectric, activates the same as that of a DRAM, and maintains recorded data, even if a power supply is cut off. Further, a time required to write data is higher than that of a non-volatile memory formed of a floating gate type of MOS transistor, which is used in the conventional flash memory.

Abstract: A non-volatile semiconductor memory device which is electrically writable and erasable is provided. The number of program/erase cycles in the non-volatile memory cells exceeds a predetermined value, a program high voltage and an erase high voltage are made higher, so that the erasing time can be shortened to achieve high-speed performance. More specifically, such a non-volatile semiconductor memory device is provided with a high-voltage generation circuit which selectively outputs a program high voltage of ±9.75 V or ±10.5 V. The high-voltage generation circuit outputs the program high voltage of ±9.75 V until the number of program/erase cycles in the non-volatile memory cells in the memory cell array exceeds a predetermined value. When the number of program/erase cycles exceeds the predetermined value, the high-voltage generation circuit outputs the program high voltage of ±10.5 V. The number of program/erase cycles is counted by a stacked-gate-type MOS transistor.

Abstract: There is provided a non-volatile memory circuit which stores information by altering a threshold voltage of memory cells so as to associate first and second threshold voltages respectively with first and second data values, and which has a first recorded state and a second recorded state different from the first recorded state such that in the first recorded state, the first and second threshold voltages are lower or higher than a first reference voltage, and in the second recorded state, the first and second threshold voltages are lower or higher than a second reference voltage different from the first reference voltage. The first or second reference voltage is set in accordance with the first and second recorded states. With the above structure, in the first recorded state, the first and second threshold voltages are either lower or higher than the first reference voltage within a voltage range lower or higher than the second reference voltage.

Abstract: In nonvolatile semiconductor memory devices, during program write operations for example, writing is accomplished by changing the threshold condition until the output from a memory cell exceeds the read verify level. During read operations, it is determined whether a target memory cell has been programmed or not by sensing whether the output from the memory cell exceeds a prescribed read level. When the data retention capability of a memory cell declines, the threshold condition of the memory cell changes. If the output of the memory cell changes to a level at which the output does not exceed the read level, the wrong data is read out. In the present invention, a monitor level which differs from the read level is established, and in the event that the output from a memory cell changes such as to approach this monitor level, this fact is sensed in advance, thereby preventing readout of wrong data.