Abstract: Magnetic readers that read magnetic data which is recorded on a magnetic card and a flexible cable that transfers each of the signals from the magnetic readers to a signal processing circuit side are included, branch portions that are branched off from a main body of the flexible cable and are connected to the magnetic readers, respectively, are provided in the flexible cable, the branch portions have first and second main-body portion side end portions, respectively, that extend in parallel to each other along a card sliding passage, and the main-body portion has a branch portion side end portion that intersects the card sliding passage and extends.

Abstract: Magnetic readers that read magnetic data which is recorded on a magnetic card and a flexible cable that transfers each of the signals from the magnetic readers to a signal processing circuit side are included, branch portions that are branched off from a main body of the flexible cable and are connected to the magnetic readers, respectively, are provided in the flexible cable, the branch portions have first and second main-body portion side end portions, respectively, that extend in parallel to each other along a card sliding passage, and the main-body portion has a branch portion side end portion that intersects the card sliding passage and extends.

Abstract: A terminal unit (201) includes: a casing (204) having a display surface with a display part (205) disposed thereon; a printer head (212) provided inside the casing (204) so as to face the display surface and adapted to print on recording paper pulled out of a recording paper roll (216); and a recording paper roll housing part (222) provided on the side opposite to the display surface across the printer head (212) so as to face the printer head (212). Due to this configuration, the terminal unit (201) can be made compact in the longitudinal direction.

Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitu

Abstract: An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

Abstract: A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; a

Abstract: An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

Abstract: A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation.