Patents by Inventor Nobuyuki Ikarashi

Nobuyuki Ikarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9362110
    Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.
    Type: Grant
    Filed: August 23, 2014
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
  • Patent number: 9263532
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: February 16, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Publication number: 20160005792
    Abstract: Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound Ta2O5 is produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound Ta2O5. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as Ta2O5) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties.
    Type: Application
    Filed: June 25, 2015
    Publication date: January 7, 2016
    Inventors: Makoto UEKI, Nobuyuki IKARASHI, Jun KAWAHARA, Kiyoshi TAKEUCHI, Takashi HASE
  • Publication number: 20150179746
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 25, 2015
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Patent number: 8975728
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Publication number: 20150014682
    Abstract: Disclosed is a semiconductor device in which the quality of an oxide semiconductor film is stabilized, while the property that an oxide semiconductor has high mobility is being utilized. The semiconductor device includes an oxide semiconductor layer and an electrode. The electrode is coupled to one surface of the oxide semiconductor layer. A portion of the oxide semiconductor layer, spanning from the one surface to a depth of t, becomes an ordered layer. The ordered layer is an area including a plurality of ordered regions in each of which the arrangement of atoms is compliant with a specific rule. The maximum width of the ordered region in a section in a direction perpendicular to the one surface is 2 nm or less.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: Nobuyuki Ikarashi, Kishou Kaneko, Kiyoshi Takeuchi
  • Publication number: 20140363982
    Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.
    Type: Application
    Filed: August 23, 2014
    Publication date: December 11, 2014
    Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
  • Patent number: 8872234
    Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
  • Publication number: 20130092949
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 18, 2013
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Patent number: 8368175
    Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 5, 2013
    Assignee: NEC Corporation
    Inventors: Takashi Nakagawa, Kaoru Mori, Nobuyuki Ikarashi, Makiko Oshida
  • Patent number: 8203176
    Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
  • Publication number: 20120104614
    Abstract: A semiconductor device manufacturing method which prevents the resistance of a Ni silicide layer from increasing due to an additive element. First, a reaction control layer which contains a metallic element with an atomic number greater than Ni and does not contain Ni is formed over a silicon layer. Then, Ni is deposited over the reaction control layer and the silicon layer, reaction control layer and Ni are heat-treated to form a Ni silicide layer in the silicon layer. It is preferable that the reaction control layer be comprised of a metallic element with an atomic number greater than Ni.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 3, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuyuki IKARASHI, Motofumi SAITOH, Kouji MASUZAKI
  • Publication number: 20120061844
    Abstract: A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 15, 2012
    Applicant: NEC CORPORATION
    Inventors: Makoto UEKI, Masayuki HIROI, Nobuyuki IKARASHI, Yoshihiro HAYASHI
  • Publication number: 20110193145
    Abstract: It is possible to achieve the above interface structure stabilization by forming a structure in which a fraction of Ni atoms are substituted with Pt atoms only in the first interface layer, thereby lowering the interface energy while suppressing the variation of the characteristics of NiSi and NiSi/Si interface to the minimum extent. Therefore, it is possible to contribute to the improvement of the yield ratio of elements or the improvement of reliability through the stabilization of the crystal phase of NiSi. The NiSi is formed, for example, on the surface layer of a source drain in a transistor.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuyuki IKARASHI, Mitsuru NARIHIRO
  • Patent number: 7968463
    Abstract: A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: June 28, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakagawa, Toru Tatsumi, Makiko Oshida, Nobuyuki Ikarashi, Kensuke Takahashi, Kenzo Manabe
  • Publication number: 20110018100
    Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.
    Type: Application
    Filed: March 27, 2009
    Publication date: January 27, 2011
    Inventors: Takashi Nakagawa, Kaoru Mori, Nobuyuki Ikarashi, Makiko Oshida
  • Publication number: 20100320520
    Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
    Type: Application
    Filed: February 4, 2008
    Publication date: December 23, 2010
    Inventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
  • Patent number: 7812412
    Abstract: According to the present invention, a semiconductor device having a field effect transistor is provided. The field effect transistor comprises a gate insulating film 2 formed on a semiconductor layer 1 and a gate electrode 5 formed on the gate insulating film 2. The gate insulating film 2 has a silicon oxide film including a metal element 4 and nitrogen 3, and characteristics of the silicon oxide film are modified by adding the metal element 4 and nitrogen 3. Respective concentration distributions of the metal element 4 and nitrogen 3 in the gate insulating film 2 have maximum values on an interface side between the gate insulating film 2 and the gate electrode 5, and gradually decrease toward the semiconductor layer 1.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: October 12, 2010
    Assignee: NEC Corporation
    Inventors: Kouji Watanabe, Nobuyuki Ikarashi, Kouji Masuzaki
  • Publication number: 20100219478
    Abstract: The present invention provides an NMOSFET including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the gate insulating film. The first gate electrode is composed of silicide of a metal M, and at least one element selected as an impurity from a group consisting of sulfur (S), fluorine (F) and chlorine (Cl). The impurity exists as an impurity layer at a surface of the first gate electrode at which the first gate electrode makes contact with the gate insulating film.
    Type: Application
    Filed: December 25, 2006
    Publication date: September 2, 2010
    Applicant: NEC Corporation
    Inventors: Kenzo Manabe, Nobuyuki Ikarashi
  • Publication number: 20090267163
    Abstract: According to the present invention, a semiconductor device having a field effect transistor is provided. The field effect transistor comprises a gate insulating film 2 formed on a semiconductor layer 1 and a gate electrode 5 formed on the gate insulating film 2. The gate insulating film 2 has a silicon oxide film including a metal element 4 and nitrogen 3, and characteristics of the silicon oxide film are modified by adding the metal element 4 and nitrogen 3. Respective concentration distributions of the metal element 4 and nitrogen 3 in the gate insulating film 2 have maximum values on an interface side between the gate insulating film 2 and the gate electrode 5, and gradually decrease toward the semiconductor layer 1.
    Type: Application
    Filed: September 21, 2006
    Publication date: October 29, 2009
    Inventors: Kouji Watanabe, Nobuyuki Ikarashi, Kouji Masuzaki