Abstract: A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor "2.sup.n -1" or "2.sup.n ", upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor "2.sup.n -1" or "2.sup.n " according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

Abstract: A frequency dividing ratio setting device capable of successively changing the frequency dividing ratio of a programmable counter and further changing the changed portion of the frequency dividing ratio is provided. The device comprises a circuit for generating a pulse signal corresponding to predetermined data, an adder-subtracter having first and second input terminals and adding or subtracting data supplied to first and second input terminals thereof, said first input terminal being connected to the output terminal of the pulse signal generating circuit, and a shift register to which an output signal is supplied from the adder-subtracter and supplying an input signal to a program terminal of the programmable counter and to the second input terminal of the adder-subtracter.

Abstract: A phase detector circuit having four dominant type flip-flop circuits and at least one logic gate. The phase detector circuit is responsive to changes of two input signals, and produces output signals related to the relative phase of the input signals having duty cycle. The output signals have a predetermined level only for the period the phases of the input signals differ. When the phases of the input signals are the same, the output signals of the phase detector circuit will be at another level.