Abstract: A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.

Abstract: An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.

Abstract: An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.

Abstract: A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.

Abstract: A semiconductor memory device operating in synchronization with an external clock signal, includes memory cells arrayed in two dimension, word lines and bit lines connected to the memory cells, IO lines connected to the bit lines, and a sense amplifier connected to the IO lines and activated by a sense amplifier enable signal. After the word line is selected, an internal clock signal is generated by delaying the rising and falling edges of the external clock signal input to the memory device. A timing at which the internal clock signal changes from a first state to a second state is delayed by a predetermined time to make the sense amplifier enable signal active, and a timing at which the internal clock signal changes from the second state to the first state is delayed by a shorter period than the predetermined time to make the sense amplifier enable signal inactive.

Abstract: A load circuit for coupling a bit line pair BLP in a memory cell array to a power supply potential makes a bit line once to a floating state when the mode shifts to a standby mode in accordance with a chip select signal /CS. The load circuit holds the potential of the bit line BL in a latch circuit and determines whether the bit line BL is coupled to the power supply potential or not in accordance with the held potential. Therefore, in the case where a small short circuit occurs between the bit line and the ground line, the bit line is disconnected from the power supply potential, thereby enabling the current in the standby mode to be reduced.

Abstract: A load circuit for coupling a bit line pair BLP in a memory cell array to a power supply potential makes a bit line once to a floating state when the mode shifts to a standby mode in accordance with a chip select signal /CS. The load circuit holds the potential of the bit line BL in a latch circuit and determines whether the bit line BL is coupled to the power supply potential or not in accordance with the held potential. Therefore, in the case where a small short circuit occurs between the bit line and the ground line, the bit line is disconnected from the power supply potential, thereby enabling the current in the standby mode to be reduced.

Abstract: A current limiter includes: a P type MOS transistor electrically coupled between a main power potential supply line supplying power supply potential Vcc and a power potential supply line; and a level converter generating a control signal of signal levels in an operating state and a standby state, respectively, corresponding to a ground potential Vss and an intermediate potential Vhh (Vss<Vhh<Vcc) adjustable externally. The control signal is inputted into the gate of the transistor. The transistor supplies a sufficient operating current for ensuring an operating margin and a standby current of a prescribed value or less satisfying a requirement for lower power consumption onto the power potential supply line in the operating state and the standby state, respectively.

Abstract: A current limiter includes: a P type MOS transistor electrically coupled between a main power potential supply line supplying power supply potential Vcc and a power potential supply line; and a level converter generating a control signal of signal levels in an operating state and a standby state, respectively, corresponding to a ground potential Vss and an intermediate potential Vhh (Vss<Vhh<Vcc) adjustable externally. The control signal is inputted into the gate of the transistor. The transistor supplies a sufficient operating current for ensuring an operating margin and a standby current of a prescribed value or less satisfying a requirement for lower power consumption onto the power potential supply line in the operating state and the standby state, respectively.

Abstract: A semiconductor memory device of the present invention includes a data bus and an I/O line which are hierarchically provided data lines. In accordance with a column selection operation, storage data in a memory cell is transmitted from the I/O line through a data bus driver to the data bus. Prior to the column selection operation, the data bus is equalized by an equalization circuit. The equalization circuit includes an equalization capacitor for holding in advance a potential corresponding to an inverted state of the data bus, and a transistor gate for connecting the equalization capacitor and the data bus.

Abstract: In a memory cell region, there are formed a pair of driver transistors and a pair of access transistors. On an insulating layer covering these transistors, there are formed a pair of high resistances. To cover the high resistances, there is formed an insulating layer. On the insulating layer, there is formed a word line. To cover the word line, there is formed an insulating layer and, on the insulating layer, there are formed a GND wiring and bit lines. Thereby, a semiconductor memory device capable of stabilized operation even when a lowered power source voltage is used can be obtained.

Abstract: NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.

Abstract: A memory cell region is provided with a pair of driver transistors as well as a pair of access transistors. Each of the access transistors is formed of a field effect transistor having a gate electrode layer. An insulating layer is formed over the driver transistors and access transistors, and is provided with contact holes located within the memory cell region and reaching the gate electrode layers. Conductive layers are formed on the insulating layer, and are in contact with the gate electrode layers through the contact holes. Thereby, a memory cell structure of an SRAM has a small planar layout area and thus is suitable to high integration.

Abstract: A power supply voltage level detecting circuit includes a reference voltage generating circuit for generating a constant reference voltage independent of a power supply voltage, a to-be-compared voltage generating circuit for generating a voltage to be compared changing dependent upon the power supply voltage, a current mirror type differentially amplifying circuit for amplifying differentially the reference voltage and the voltage to be compared, and a determining circuit for generating a level detecting signal indicating whether or not the power supply voltage has attained a predetermined level in accordance with an output of the differentially amplifying circuit. The to-be-compared voltage generating circuit generates the voltage to be compared by dropping the power supply voltage using the resistance division or the forward voltage drop of diode.