Patents by Inventor Nobuyuki Ooya

Nobuyuki Ooya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked single crystal compound semiconductor substrates
    Patent number: 8704340
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 22, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20130306977
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Application
    Filed: March 25, 2013
    Publication date: November 21, 2013
    Applicant: DENSO CORPORATION
    Inventors: Hiroaki FUJIBAYASHI, Masami NAITO, Nobuyuki OOYA
  • Single crystal compound semiconductor substrate
    Patent number: 8507921
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20120181550
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 19, 2012
    Applicant: DENSO CORPORATION
    Inventors: Hiroaki FUJIBAYASHI, Masami Naito, Nobuyuki Ooya
  • MIS type semiconductor device and method for manufacturing same
    Patent number: 5877531
    Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: March 2, 1999
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigemitsu Fukatsu, Ryoichi Kubokoya, Kenji Shiratori, Nobuyuki Ooya
  • MIS type semiconductor device and method for manufacturing same
    Patent number: 5834347
    Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: November 10, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigemitsu Fukatsu, Ryoichi Kubokoya, Kenji Shiratori, Nobuyuki Ooya