Patents by Inventor Nobuyuki Sugii
Nobuyuki Sugii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10410826Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.Type: GrantFiled: March 18, 2016Date of Patent: September 10, 2019Assignee: HITACHI, LTD.Inventors: Tetsufumi Kawamura, Misuzu Sagawa, Kazuki Watanabe, Keiji Watanabe, Shuntaro Machida, Nobuyuki Sugii, Daisuke Ryuzaki
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Publication number: 20190244659Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
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Patent number: 10336609Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.Type: GrantFiled: June 1, 2017Date of Patent: July 2, 2019Assignee: Hitachi, Ltd.Inventors: Keiji Watanabe, Shuntaro Machida, Katsuya Miura, Aki Takei, Tetsufumi Kawamura, Nobuyuki Sugii, Daisuke Ryuzaki
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Patent number: 10311943Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: GrantFiled: February 5, 2018Date of Patent: June 4, 2019Assignee: Renesas Electronics CorporationInventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
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Patent number: 10203688Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.Type: GrantFiled: May 12, 2017Date of Patent: February 12, 2019Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Nobuyuki Sugii, Tomonori Sekiguchi, Shuntaro Machida, Tetsufumi Kawamura
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Publication number: 20190013179Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.Type: ApplicationFiled: March 18, 2016Publication date: January 10, 2019Applicant: HITACHI, LTD.Inventors: Tetsufumi KAWAMURA, Misuzu SAGAWA, Kazuki WATANABE, Keiji WATANABE, Shuntaro MACHIDA, Nobuyuki SUGII, Daisuke RYUZAKI
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Publication number: 20180273378Abstract: Provided is a technology that enables the shortening of the designing period. A device designing method includes a step of extracting a structure compatible with requested characteristics from a database in which each structure of a device is associated with characteristics and a step of outputting the extracted structure and a tuning parameter for adjusting the structure into ranges of the requested characteristics. In regard to each structure parameter determining the structure of the device, characteristics obtained by performing a simulation while exhaustively changing the structure parameter in a manufacturable range and the structure parameter used for the simulation are stored in the database while being associated with each other.Type: ApplicationFiled: March 18, 2016Publication date: September 27, 2018Inventors: Tetsufumi KAWAMURA, Kazuki WATANABE, Atsushi ISOBE, Yuudai KAMADA, Shuntaro MACHIDA, Nobuyuki SUGII, Daisuke RYUZAKI
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Publication number: 20180267075Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.Type: ApplicationFiled: March 18, 2016Publication date: September 20, 2018Inventors: Shuntaro MACHIDA, Nobuyuki SUGII, Keiji WATANABE, Daisuke RYUZAKI, Tetsufumi KAWAMURA, Kazuki WATANABE
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Publication number: 20180158512Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: ApplicationFiled: February 5, 2018Publication date: June 7, 2018Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
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Publication number: 20180137212Abstract: Provided is a device design support apparatus in which a data input-output portion receives an input of a first device provisional specification relating to a device from a customer, a database generating portion generates a second database based on a first database stored in a database storing portion and the first device provisional specification, and a device specification generating portion generates a second device provisional specification relating to the device based on the second database, presents the second device provisional specification to the customer by outputting the generated second device provisional specification through the data input-output portion, receives the input of a change content of the second device provisional specification from the customer, and generates a device fixed specification of the device based on the second device provisional specification and the change content.Type: ApplicationFiled: November 8, 2017Publication date: May 17, 2018Applicant: HITACHI, LTD.Inventors: Yuhua ZHANG, Tetsufumi KAWAMURA, Atsushi ISOBE, Nobuyuki SUGII, Daisuke RYUZAKI
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Publication number: 20180121569Abstract: A customer's request is more appropriately reflected in the design. A method of processing a request for designing a device receives a required specification for a device from a user input and output device, searches a case similar to the required specification in the old case specification information, outputs the case similar to the required specification found in the old case specification information to the user input and output device, and calculates a specification of a design result of the device according to the required specification for an unauthorized input for the similar case from the user input and output device, or transmits a request for designing the device according to the required specification to an external design system, and outputs the design result of the device calculated or received from the design system to the user input and output device.Type: ApplicationFiled: October 17, 2017Publication date: May 3, 2018Inventors: Futoshi FURUTA, Nobuyuki SUGII, Daisuke RYUZAKI
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Publication number: 20180121589Abstract: The present invention provides a technique for determining the circuit configuration and device structure that meet required specifications in a short time. A device design support method includes: a step (S2) of receiving an input of specifications of a sensor, and extracting the circuit configuration and device specification range corresponding to the received specifications of the sensor, by referring to a circuit design database in which the circuit configuration configuring the sensor, the range of the specifications of the device configuring the sensor, and the specifications of the sensor are associated with each other; and a step (S3) of extracting the device structure corresponding to the extracted device specification range by referring to a device design database in which the specifications of the device and the structure of the device are associated with each other.Type: ApplicationFiled: October 19, 2017Publication date: May 3, 2018Inventors: Tetsufumi KAWAMURA, Nobuyuki SUGII, Yuudai KAMADA, Yuhua ZHANG, Atsushi ISOBE, Ryohei MATSUI, Daisuke RYUZAKI
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Patent number: 9959924Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: GrantFiled: March 3, 2017Date of Patent: May 1, 2018Assignee: Renesas Electronics CorporationInventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
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Publication number: 20180017958Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.Type: ApplicationFiled: May 12, 2017Publication date: January 18, 2018Inventors: Masaharu KINOSHITA, Nobuyuki SUGII, Tomonori SEKIGUCHI, Shuntaro MACHIDA, Tetsufumi KAWAMURA
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Publication number: 20170362082Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.Type: ApplicationFiled: June 1, 2017Publication date: December 21, 2017Inventors: Keiji WATANABE, Shuntaro MACHIDA, Katsuya MIURA, Aki TAKEI, Tetsufumi KAWAMURA, Nobuyuki SUGII, Daisuke RYUZAKI
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Publication number: 20170178717Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
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Patent number: 9646679Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: GrantFiled: November 25, 2015Date of Patent: May 9, 2017Assignee: Renesas Electronics CorporationInventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
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Publication number: 20160180923Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.Type: ApplicationFiled: November 25, 2015Publication date: June 23, 2016Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
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Patent number: 8878244Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.Type: GrantFiled: January 3, 2008Date of Patent: November 4, 2014Assignee: Renesas Electronics CorporationInventors: Yasuichi Kondo, Wataru Hirasawa, Nobuyuki Sugii
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Patent number: 8680553Abstract: An object of the present invention is to provide a germanium laser diode that can be easily formed on a substrate such as silicon by using a normal silicon process and can emit light efficiently. A germanium light-emitting device according to the present invention is a germanium laser diode characterized in that tensile strain is applied to single-crystal germanium serving as a light-emitting layer to be of a direct transition type, a thin semiconductor layer made of silicon, germanium or silicon-germanium is connected adjacently to both ends of the germanium light-emitting layer, the thin semiconductor layer has a certain degree of thickness capable of preventing the occurrence of quantum confinement effect, another end of the thin semiconductor layer is connected to a thick electrode doped with impurities at a high concentration, the electrode is doped to a p type and an n type, a waveguide is formed so as not to be in direct contact with the electrode, and a mirror is formed at an end of the waveguide.Type: GrantFiled: October 21, 2009Date of Patent: March 25, 2014Assignee: Hitachi, Ltd.Inventors: Shinichi Saito, Masahiro Aoki, Nobuyuki Sugii, Katsuya Oda, Toshiki Sugawara