Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

Abstract: A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.

Abstract: A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.

Abstract: In an embodiment, a PWM modulation circuit includes a first circuit block configured to receive a square wave input signal and produce from the square wave input signal a triangular wave signal, a second circuit block configured to receive a modulating signal and produce a PWM signal by comparing the modulating signal with a carrier signal, a switching circuit block coupled between the first circuit block and the second circuit block and sensitive to reference signals having upper and lower reference values and selectively switchable between a carrier transfer setting in which the switching circuit block couples the first circuit block to the second circuit block to transfer the triangular wave signal as the carrier signal, and one or more carrier forcing settings for optimizing or inhibiting pulse skipping in the PWM signal, wherein the switching circuit block forces the carrier signal to the upper and lower reference values, respectively.

Abstract: In an embodiment, a PWM modulation circuit includes a first circuit block configured to receive a square wave input signal and produce from the square wave input signal a triangular wave signal, a second circuit block configured to receive a modulating signal and produce a PWM signal by comparing the modulating signal with a carrier signal, a switching circuit block coupled between the first circuit block and the second circuit block and sensitive to reference signals having upper and lower reference values and selectively switchable between a carrier transfer setting in which the switching circuit block couples the first circuit block to the second circuit block to transfer the triangular wave signal as the carrier signal, and one or more carrier forcing settings for optimizing or inhibiting pulse skipping in the PWM signal, wherein the switching circuit block forces the carrier signal to the upper and lower reference values, respectively.