Abstract: A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and sets up and clears the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, a signal for enabling idle detector control of the CPU stop clock interrupt mode and a signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system.