Abstract: A signal generator generates a first internal signal including frequency f1, a second internal signal including frequency f2, and a third internal signal including frequency f3 twice as high as frequency f2, and selects and delivers one from among a first output signal including frequency f1, a second output signal including frequency f1+f2, and a third output signal including frequency f1+f3, using the first, second, and third internal signals.

Abstract: A frequency synthesizer includes compensation variable capacitance diodes 53 and 54 in a voltage-controlled oscillator 5 in addition to a variable capacitance diode 52 whose DC bias voltage is controlled by a control voltage signal 11 generated by a low-pass filter 3. A monitor circuit 8 monitors the control voltage signal 11 and changes the level of control signals 16 and 17 when the voltage of the control voltage signal 11 goes out of a range within which the capacitance of the variable capacitance diode 52 can be easily changed. A time constant circuit 72 supplies a DC bias voltage to the compensation variable capacitance diode for smoothing out the level change of the control signals 16 and 17 into a slow voltage change so that a locked state is not canceled.

Abstract: Output conductance of a differential current output type circuit constituting a filter body (1) and having a variable negative resistor connected between differential output lines is automatically regulated. The output conductance automatic regulation circuit comprises a differential voltage/current conversion circuit (2) which is a replica of a differential voltage/current conversion circuit constituting the filter body (1), a variable negative resistor (3) connected between the differential output lines of the differential voltage/current conversion circuit (2), a detector (4) for detecting the DC potential difference between the differential output lines of the differential voltage/current conversion circuit (2), and a controller (5) for controlling the differential voltage/current conversion circuit (2) and the conductance of a variable negative resistor connected with the differential voltage/current conversion circuit constituting the filter body (1) based on the detection results from the detector (4).

Abstract: An inverse temperature characteristic generating circuit decreases an output voltage Vout by a voltage VGS, and supplies the resultant voltage as a voltage VA to a temperature characteristic generating circuit. The temperature characteristic generating circuit includes a differential amplification circuit that receives a terminal voltage VAP between resistances R22 and R23 and an emitter voltage VAM of a bipolar transistor T21, and outputs a control signal VC. When the terminal voltages VAP and VAM are equal to each other, an operation of a circuit is stable. The temperature characteristic of the voltage VA during the stable operation, and the temperature characteristic of the voltage VGS are inverse to each other and therefore cancel each other, so that the constant voltage Vout independent of temperature is output. In addition, the output terminal is not connected via a resistance to a ground, so that low current consumption can be easily achieved.

Abstract: A signal processing device suppresses a DC offset without omission of a low-frequency component of a signal in a receiver in a direct conversion system. The signal processing device includes an input terminal 29, a gain amplifier 31 that amplifies an input signal to generate an output signal, comparators 32 and 33 each of which compares an output signal level with a reference value, a capacitor 37, current source circuits 34 and 35, one of which charges or discharges electric charges stored in the capacitor when the output signal level falls outside a reference range according to results of comparisons by the comparators, a variable current source 36 through which current to be flow is controlled according to a potential at the capacitor, and a load circuit 38 that is connected between the input terminal and the variable current source and supplies a bias to the input terminal, together with the variable current source.

Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Abstract: An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the information processing device in accordance with manipulation by a user, and a controller that controls the information processing device to transfer data in a mode in which data temporarily stored in a data storing area is transferred to the storage or in a mode in which data is transferred to the storage without being temporarily stored in the data storing area in accordance with the selection of the data transfer mode by the switch unit.

Abstract: A signal processing unit of the present invention includes: input terminal (21) to which an input signal is input; high-pass filter (23) for cutting off the DC component of the input signal; output terminal (22) for outputting a signal output from high-pass filter (23) as an output signal; determination element (26) for determining whether or not the voltage of the output signal falls out of a predetermined detection threshold range; and, switches (27,28) for connecting the output node of high-pass filter (23) to a power supply circuit when the voltage of the output signal is determined to fall out of the detection threshold range at determination element (26).

Abstract: A signal generator generates a test signal including a positive signal and a negative signal which have the same amplitude. The signal generator corrects a DC level of the test signal based on a DC offset correcting signal supplied thereto, and supplies the corrected test signal to a frequency converter. An amplitude detector detects the amplitudes of the positive and negative signals of the test signal processed by the frequency converter. A level compressor converts in level the amplitudes of the positive and negative signals which are detected by the amplitude detector, with a gain variable depending on an input level thereto. A comparator compares the amplitudes of the positive and negative signals which are converted in level by the level compressor, with each other. An offset adjuster supplies the DC offset correcting signal depending on a compared result from the comparator to the signal generator.

Abstract: The semiconductor device of the present invention includes: first defensive wiring provided above a diffusion isolation layer formed in a substrate or a well, arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer; a plurality of signal wiring layers formed above the first defensive wiring; and means for applying a predetermined signal to the first defensive wiring and capturing a change in an electrical or physical property of the first defensive wiring.

Abstract: An inverse temperature characteristic generating circuit decreases an output voltage Vout by a voltage VGS, and supplies the resultant voltage as a voltage VA to a temperature characteristic generating circuit. The temperature characteristic generating circuit includes a differential amplification circuit that receives a terminal voltage VAP between resistances R22 and R23 and an emitter voltage VAM of a bipolar transistor T21, and outputs a control signal VC. When the terminal voltages VAP and VAM are equal to each other, an operation of a circuit is stable. The temperature characteristic of the voltage VA during the stable operation, and the temperature characteristic of the voltage VGS are inverse to each other and therefore cancel each other, so that the constant voltage Vout independent of temperature is output. In addition, the output terminal is not connected via a resistance to a ground, so that low current consumption can be easily achieved.

Abstract: Provided is a reference current circuit able to reduce temperature dependence of the reference current even in a case of using a resistor with extremely low temperature-dependent resistance. The reference current circuit comprises a non-inverting amplifier circuit 110 receiving a temperature-compensated reference voltage VBG and generating a voltage Vout1 at an output point; a current source circuit 120 composed of a transistor Q1 connected to the output point via a resistor and a transistor Q2 receiving a voltage equal to a voltage VBE1 generated across terminals of Q1 and generating a corresponding current. The circuit 110 (i) includes a third transistor Q3, a voltage VBE3 generated across terminals of which has the same temperature characteristic as the voltage VBE1, and (ii) is configured such that Vout1 is a sum of (a) a temperature-compensated voltage component based on VBG and (b) a voltage component equal-to-the voltage VBE3.

Abstract: Signal processing apparatus or non-integer divider with a small circuit scale and a fractional N-PLL synthesizer comprising same. An adder 2 and a delay device 4 constitute a 20-bit input accumulator and its input is connected to a signal input terminal 1. Adder 8 and a delay device 10 constitute a 9-bit input accumulator. Into higher 8 bits of its input, higher 8 bits of the output of the accumulator comprising the adder 2 and the delay device 4 are inputted. The output of a 3-input NAND gate 30 is connected to the remaining lowest bit input. An adder 13 and a delay device 15 constitute a 6-bit input accumulator. Higher 6 bits of an output signal of the adder 8 are inputted into this 6-bit input accumulator. An adder 18 and a delay device 20 constitute a 4-bit input accumulator. Higher 4 bits of an output signal of the adder 13 are inputted into this 4-bit input accumulator. Lower 3 bits of output data of the 4-bit delay device 20 are inputted into the 3-input NAND gate 30.

Abstract: A data carrier system includes: a first memory, which is a ferroelectric memory; a second memory; a polarization canceling circuit for canceling polarization of the first memory in accordance with an instruction given thereto; and a control circuit for making data access to the first and second memories and controlling operation of the polarization canceling circuit. Upon receipt of a first instruction, the control circuit saves data stored in the first memory to the second memory and then gives an instruction for canceling polarization to the polarization canceling circuit, while upon receipt of a second instruction, the control circuit writes the data saved to the second memory back into the first memory.

Abstract: A test signal, the amplitudes of which are equal in the positive and negative directions, is generated and supplied to a signal processing circuit that performs a frequency conversion. Signals outputted from the signal processing circuit are detected to provide detected signals, which comprise a detected positive signal corresponding to a positive signal of the test signal and a detected negative signal corresponding to a negative signal of the test signal. The level of the detected positive signal is compared with the level of the detected negative signal to output a comparison result that indicates which level is higher. Additionally, an offset correction signal, which causes the level difference between the detected positive signal and the detected negative signal to be within a predetermined range of tolerance, is generated based on the comparison result. Then, an offset correction of the test signal and an externally supplied modulated signal is performed in accordance with the offset correction signal.

Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

Abstract: A signal input into an input terminal 1 is input into mixers 2, 4, and down-converted with local signals having a phase difference of 90 degrees, respectively, whereby an I-signal and a Q-signal are obtained. An output signal from the mixer 4 is delayed 90 degrees in phase by a phase shifter 6. An adder 7 outputs a sum signal of the I-signal and the Q-signal, and a subtracter 8 outputs a subtracted signal between the I-signal and the Q-signal. The sum signal and the subtracted signal are input into band pass filters 9, 10, in which signals in undesired frequency band are cut, then converted into digital signals by AD converters 11, 12 and input into a signal processor 13. In the signal processor 13, a correlation signal of the sum signal and the subtracted signal is formed, and an image signal included in the sum signal is removed using the correlation signal and the subtracted signal.

Abstract: A signal processing unit of the present invention includes: input terminal (21) to which an input signal is input; high-pass filter (23) for cutting off the DC component of the input signal; output terminal (22) for outputting a signal output from high-pass filter (23) as an output signal; determination element (26) for determining whether or not the voltage of the output signal falls out of a predetermined detection threshold range; and, switches (27,28) for connecting the output node of high-pass filter (23) to a power supply circuit when the voltage of the output signal is determined to fall out of the detection threshold range at determination element (26).

Abstract: The ferroelectric memory apparatus stores data, and includes: a ferroelectric memory element; a temperature sensor which detects a temperature of the apparatus; a control unit that outputs a control signal indicating a voltage, the voltage increasing as the temperature detected by the temperature sensor decreases; and a voltage generating unit that generates the voltage indicated by the control signal outputted by the control unit, and to supply the generated voltage to the ferroelectric memory element. This provides a ferroelectric memory apparatus which can recover from effects of thermal stress suffered after shipment—i.e., reduction in the polarization amount needed for data retention as well as imprint degradation—using a relatively simple configuration.

Abstract: A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.