Abstract: A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.

Abstract: The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Abstract: A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.

Abstract: An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being generated and retaining a processing speed of the device. To this end, according to the present invention, there is provided a device including logic blocks for carrying out logical operation, lines for connecting the logic blocks, line-changing means for changing the state of lines connecting the logic blocks by programming, a clock net for supplying a clock signal to each of the logic blocks, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of the logic blocks can be stopped from being supplied with the clock signal.

Abstract: An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being generated and retaining a processing speed of the device. To this end, according to the present invention, there is provided a device including logic blocks for carrying out logical operation, lines for connecting the logic blocks, line-changing means for changing the state of lines connecting the logic blocks by programming, a clock net for supplying a clock signal to each of the logic blocks, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of the logic blocks can be stopped from being supplied with the clock signal.

Abstract: A newspaper dealer server is provided with at least a contractor data base that registers contractors who have subscriber contracts with a newspaper dealer. An advertisement preparation unit of the server prepares an advertisement that is requested from an advertiser, and places it in an advertisement Web page. Upon finding that a user is a contractor on the contractor data base through an input of the user information, an advertisement utilization unit of the server publicizes the advertisement Web page and allows the user to view it.

Abstract: A processor architecture includes a program counter which executes M independent program streams in time division in units of one instruction, a pipeline which is shared by each of the program streams and has N pipeline stages operable at a frequency F, and a mechanism which executes only s program streams depending on a required operation performance, where M and N are integers greater than or equal to one and having no mutual dependency, s is an integer greater than or equal to zero and satisfying s≦M. An apparent number of pipeline stages viewed from each of the program streams is set to N/M so that M parallel processors having an apparent operating frequency F/M are formed.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Abstract: A processor is efficiently controlled and the electric power required to drive the processor is reduced by switching between a process of driving a plurality of arithmetic units using a series of instructions from an instruction control unit and a process of driving a plurality of arithmetic units using a plurality of series of instructions from different instruction control units according to an object to be processed. When a plurality of instruction control units 10, 11 and 12 drive a plurality of arithmetic units 13, 14 and 15, a synchronous execution process of driving the plurality of arithmetic units 13, 14 and 15 using the series of instructions from the first instruction control unit 10 is switched to/from an independent execution process of driving the arithmetic units 13, 14 and 15 using the series of instructions from the instruction control units 10, 11 and 12, respectively, according to the information contained in the series of instructions.

Abstract: A simulator can simulate a processor which performs pipeline processing of operation instructions, and performs operation processes in parallel, a number of the processes being larger than a number of the pipelines. The simulator simulates a passing operation in which a result of an operation processing obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.