Abstract: A system transmits data between two semiconductor devices which are different from each other. The data modules either the amplitude or the amplitude and current of a synchronous transmit clock pulse train. The transmitted data is sent and received on one line.

Abstract: A semiconductor memory device having a controllable majority decision reading scheme is disclosed. The memory is featured in that a number of memory cells to be selected in one access cycle is varied by at least one control signal and a logic state of a read-out signal is determined by data derived from the desired number of memory cell on cells.

Abstract: A nonvolatile memory (programmable) comprises a plurality of logic memories, each of which is composed of a plurality of memory segments. Each of the memory segments is constituted of a first nonvolatile memory area capable of storing data of a predetermined bit number and a second nonvolatile memory area containing an identifier for the corresponding first nonvolatile memory area. Each of the logical memories is given one logical address, and when write operation is executed, a controller operates to access to the logical memory identified by the inputted logical address so as to erase in the accessed logical memory the memory segment having the identifier indicating that the data is stored, and to write the inputted data to the memory segment next to the erased memory segment.

Abstract: An integrated circuit device having a memory. A plurality of identical versions of a given piece of data may be stored at different addresses in the memory, and portions thereof read out in time-division fashion through a reduced number of sense amplifiers and common signal lines to majority logic circuitry, so as to enhance reliability while at the same time reducing the amount of area required on an integrated circuit chip.

Abstract: An 8.5 divider comprises a first and second 1/2 dividers to produce output pulses having phases different from each other by 90.degree., a first logic gate producing output pulses having a repetition frequency of a half of the input pulses, a third and fourth 1/2 dividers connected in series and dividing twice the output pulses of the first logic gate by two, a fifth 1/2 divider receiving the output of the fourth 1/2 divider, a second logic gate detecting the simultaneous presence of the outputs of the second, third and fifth 1/2 dividers to invert the phase of the output pulses of the first 1/2 divider and a third logic gate detecting the simultaneous presence of the outputs of the first and third 1/2 dividers and the inverted output of the fifth 1/2 divider.

Abstract: A process for manufacturing a flexible cylindrical body includes the steps of providing a flexible preform of non-resilient synthetic material which is inflatable to cylindrical form, inserting the preform into an elongated coil of an electrically conductive material having a diameter relative to that of the preform in its inflated cylindrical form such that the preform is expanded in an unstressed condition into engagement with the inner diameter of the coil, the inner face of the coil being coated with an adhesive material, and applying a predetermined voltage to the coil to thereby fuse the adhesive material and connect the coil and preform.