Patents by Inventor Norihiko Kasai
Norihiko Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6875639Abstract: A semiconductor chip has a quadrangle main surface, a wiring substrate, and a resin seal member for sealing the semiconductor chip, in which the resin seal member has a quadrangle main surface which confronts the main surface of the semiconductor chip. A gate cut trace portion is formed on a side face extending along a first side of the main surface of the resin seal member. A sectional area of an area between the main surface of the wiring substrate and the main surface of the resin seal member at a position outside a side face of the semiconductor chip is smaller than a sectional area of an area between the main surface of the semiconductor chip and the main surface of the resin seal member.Type: GrantFiled: March 7, 2002Date of Patent: April 5, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Hiroshi Arai, Nobuaki Nagashima, Norihiko Kasai, Isao Seki
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Patent number: 6835596Abstract: An improvement of the yield of semiconductor devices is achieved in the manufacture of a semiconductor device. The method includes forming a resin enclosure for block-molding a plurality of a semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate, and then injecting a resin from a first side to a second side of a main surface of the substrate. The plurality of semiconductor chips are mounted on the main surface of the substrate from the first side to the second side of the main surface with a predetermined spacing, the second side facing the first side. The method is characterized by the application of cleaning treatment to the main surface of the substrate before forming the resin enclosure.Type: GrantFiled: September 28, 2001Date of Patent: December 28, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Masakatsu Gotou, Norihiko Kasai
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Patent number: 6767767Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.Type: GrantFiled: July 16, 2002Date of Patent: July 27, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Tetsuya Hayashida, Norihiko Kasai
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Publication number: 20030145461Abstract: A semiconductor device is disclosed which can prevent the leakage of resin and improve the production efficiency. The semiconductor device comprises a substrate, the substrate having plural connecting terminals formed around a recess and plural bump lands arranged side by side around the connecting terminals, a semiconductor chip disposed in the recess, plural wires for connecting pads on the semiconductor chip and the connecting terminals on the substrate with each other, a seal portion embedded in the recess, and plural ball electrodes provided on the bump lands of the substrate. A dummy wiring covered with solder resist is formed in an area between the plural connecting terminals and the plural bump lands on the substrate. According to this construction, a gap between a mold surface of an upper mold and the surface of the substrate, which gap is formed at the time of die clamping, is filled up with the dummy wiring and the solder resist which covers the dummy wiring.Type: ApplicationFiled: October 25, 2002Publication date: August 7, 2003Inventors: Norihiko Kasai, Hiromasa Ohno
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Publication number: 20030045030Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.Type: ApplicationFiled: July 16, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Tetsuya Hayashida, Norihiko Kasai
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Publication number: 20020135056Abstract: A semiconductor device comprising a semiconductor chip having a quadrangular main surface, a wiring substrate with the semiconductor chip disposed on a main surface thereof, a resin seal member for sealing the semiconductor chip, the resin seal member having a quadrangular main surface which confronts the main surface of the semiconductor chip, and a gate cut trace portion formed on a side face extending along a first side of the main surface of the resin seal member, wherein the first side of the main surface of the resin seal member extends along a first side of the main surface of the semiconductor chip, the main surface of the resin seal member has a second side intersecting the first side thereof, the second side of the main surface of the resin seal member extending along a second side of the main surface of the semiconductor chip which second side intersects the first side of the chip main surface, and in a section orthogonal to the second side of the main surface of the semiconductor chip, a sectionalType: ApplicationFiled: March 7, 2002Publication date: September 26, 2002Inventors: Hiroshi Arai, Nobuaki Nagashima, Norihiko Kasai, Isao Seki
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Publication number: 20020038918Abstract: The improvement of the yields of semiconductor devices is intended. In a method for manufacturing a semiconductor device, it has forming a resin enclosure for block-molding a plurality of semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate and then injecting a resin from a first side to a second side of a main surface of the substrate, the plurality of semiconductor chips being mounted on the main surface of the substrate from the first side to the second side of the main surface with a predetermined space, the second side facing to the first side, the method further has applying cleaning treatment to the main surface of the substrate before forming the resin enclosure.Type: ApplicationFiled: September 28, 2001Publication date: April 4, 2002Inventors: Masakatsu Gotou, Norihiko Kasai
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Patent number: 5910010Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.Type: GrantFiled: February 18, 1997Date of Patent: June 8, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Hirotaka Nishizawa, Tomoyoshi Miura, Ichirou Anjou, Masamichi Ishihara, Masahiro Yamamura, Sadao Morita, Takashi Araki, Kiyoshi Inoue, Toshio Sugano, Tetsuji Kohara, Toshio Yamada, Yasushi Sekine, Yoshiaki Anata, Masakatsu Goto, Norihiko Kasai, Shinobu Takeura, Mutsuo Tsukuda, Yasunori Yamaguchi, Jiro Sawada, Hidetoshi Iwai, Seiichiro Tsukui, Tadao Kaji, Noboru Shiozawa