Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Abstract: In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Abstract: In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Abstract: Disclosed is an integrated circuit device comprising a startup operation circuit (101) for carrying out processing necessary for startup and a post-startup operation circuit (102) for carrying out a main operation after completion of the processing necessary for startup, wherein the post-startup operation circuit (102) has an operation guaranteed temperature whose lower limit is higher than a lower limit of an operation guaranteed temperature of the startup operation circuit (101), and the post-startup operation circuit (102) starts the main operation after a temperature of the integrated circuit device exceeds a threshold temperature which is equal to the lower limit of the operation guaranteed temperature of the post-startup operation circuit (102).

Abstract: In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Abstract: Disclosed is an integrated circuit device comprising a startup operation circuit (101) for carrying out processing necessary for startup and a post-startup operation circuit (102) for carrying out a main operation after completion of the processing necessary for startup, wherein the post-startup operation circuit (102) has an operation guaranteed temperature whose lower limit is higher than a lower limit of an operation guaranteed temperature of the startup operation circuit (101), and the post-startup operation circuit (102) starts the main operation after a temperature of the integrated circuit device exceeds a threshold temperature which is equal to the lower limit of the operation guaranteed temperature of the post-startup operation circuit (102).

Abstract: In a packet data processing determination apparatus (DBA1) for respectively and sequentially determining a plurality of packet data (P) composing an inputted transport stream (TS), a packet data storage section (270) stores the packet data (P) for a predetermined time period in the order in which they came. A stored packet data identifying section (270, 260) reads identification information (PIDe) from the stored packet data (P). A target packet data determining section (400) compares the read identification information (PIDe) with predetermined process information (PIDd) to determine whether the packet data (P) is to be processed.

Abstract: In a multi-format transport stream decoder that performs a desired process on first transport streams of different formats to generate a second transport stream, a process request information input unit (APR) is supplied with process target packet data (Pi) and process request information (ScW) indicative of process details. A stream identification information providing unit (TSRi) provides stream identification information (TSID). A packet data retaining and identifying unit (DBA) retains each pieces of first packet data (Pi), and compares the stream identification information (TSIDe) and packet data identification information (PIDe) of the first packet data (Pi) with the process request information (ScW) to determine whether the information is to be processed.

Abstract: With a temporary operating unit being operating, a user provides a boot timing using a boot timing instructing unit. This causes a CPU to compute a boot preparation timing based on the boot timing, and store the boot timing and boot preparation timing to a boot timing memory. At this time, a timer begins a time-keeping operation. After that, the user turns off the power to the temporary operating unit. A boot preparation instructing unit determines whether or not the time being measured by the timer coincides with the boot preparation timing stored in the boot timing memory. When the time measured by the timer coincides with the boot preparation timing stored in the boot timing memory, the boot preparation instructing unit provides the CPU with a boot preparation instruction. This turns on the power to the temporary operating unit, and the CPU performs a boot preparation.

Abstract: A demultiplexer circuit which can simultaneously demultiplex plural pieces of input data while minimizing the circuit scale. The demultiplexer circuit includes an input line identification information addition circuit 2 for giving input line identification information to input data which have data identification information and are inputted through plural input lines 1, respectively; a multiplexer 4 for outputting the input data which have been given the input line identification information, respectively, by the input line identification information addition circuit 2 through one common line 5; a filter 6 for filtering the data outputted from the multiplexer 4 on the basis of the input line identification information and the data identification information at one time; and a filter table 7 that contains filtering conditions which are used in the filter 6.

Abstract: A data transmitter for detecting a reference time stamp for use in reproducing a system clock from a transport packet data of a first transport stream, adding the detected reference time stamp as a header information to the transport packet data, converting the transport packet data and the header information into a second transport stream, and transmitting the second transport stream.

Abstract: With a temporary operating unit being operating, a user provides a boot timing using a boot timing instructing unit. This causes a CPU to compute a boot preparation timing based on the boot timing, and store the boot timing and boot preparation timing to a boot timing memory. At this time, a timer begins a time-keeping operation. After that, the user turns off the power to the temporary operating unit. A boot preparation instructing unit determines whether or not the time being measured by the timer coincides with the boot preparation timing stored in the boot timing memory. When the time measured by the timer coincides with the boot preparation timing stored in the boot timing memory, the boot preparation instructing unit provides the CPU with a boot preparation instruction. This turns on the power to the temporary operating unit, and the CPU performs a boot preparation.

Abstract: A demultiplexer is provided with a PID extractor for extracting a PID of each TS packet from an inputted transport stream; a PID comparator for detecting whether or not the extracted PID matches any of PIDs which are set on a PID table, and outputting an entry number of the PID table where the corresponding PID is set, as a matching PID entry number, when a match is detected; a packet selector for selecting TS packets whose PIDs are detected by the PID comparator; and a data storage controller for determining an area in a memory where each TS packet is to be stored, according to the matching PID entry number; wherein TS packets having different PIDs are multiplexed and stored into a video data storage area in the memory. Therefore, when plural kinds of video data are included in the same program on digital broadcasting, these plural kinds of video data can be reproduced simultaneously.

Abstract: The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.

Abstract: A digital broadcast data receiving apparatus comprises a plurality of broadcast data receiving units for receiving digital broadcast data supplied from a plurality of digital broadcast data sources, respectively and a parallel receiving unit for receiving, from the digital broadcast data output from the plural broadcast data receiving units, object program broadcast data which are multiplexed digital broadcast data including program broadcast data relating to an object program broadcast to be viewed by the viewer, and received broadcast data which are digital broadcast data output from the broadcast data receiving unit different from the broadcast data receiving unit which outputs the object program broadcast data.

Abstract: A first memory stores in advance, in an address assigned to each of possible values that each of the plurality of data segments can have, reference data which indicates that the possible value is consistent with the detection condition (“consistency”) or reference data which indicates that the possible value is inconsistent with the detection condition (“inconsistency”) based on the detection condition. A data extraction section sequentially extracts a data segment from the input data to supply an address corresponding to a value of the extracted data segment to the first memory. The first memory outputs reference data stored in the address supplied from the data extraction section. A determination section determines whether or not the input data is consistent with the detection condition based on the reference data output from the first memory.

Abstract: A digital communication system of the present invention comprises: a transmitter for sequentially transmitting predetermined format data; and a plurality of receivers 102 each including a data selecting apparatus 104 for selecting required data from received data group and outputting selected data.