Patents by Inventor Norihiro Kobayashi
Norihiro Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160204024Abstract: Method for manufacturing a bonded wafer, including implanting at least one gas ion into a bond wafer from a bond wafer surface forming an ion implantation layer, bonding the surface from the ion implantation into bond wafer and base wafer surface, and delaminating the bond wafer part along the ion implantation layer by heat treatment forming a bonded wafer having thin-film on the base wafer, wherein heat treatment is at most 400° C. to delaminate bond wafer part along the ion implantation layer, including measuring bond wafer thicknesses and base wafer, selecting a combination of bond and base wafers so difference between both wafers thicknesses is 5 ?m or more before bonding the bond and base wafers. Inhibition of film thickness unevenness with marble pattern caused in thin-film when a bonded wafer is manufactured by ion implantation delamination method, and can manufacture a bonded wafer having thin-film with high thickness uniformity.Type: ApplicationFiled: August 1, 2014Publication date: July 14, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro KOBAYASHI, Hiroji AGA
-
Publication number: 20160118294Abstract: Method of producing bonded wafer including thin film on base wafer, including: implanting at least one gas ion selected from hydrogen ion and rare gas ion into bond wafer from surface of bond wafer to form layer of implanted ion; bonding surface from which ion is implanted into bond wafer and surface of base wafer directly or through insulator film; and then performing heat treatment to separate part of bond wafer along layer of implanted ion, wherein before bond wafer and base wafer are bonded, thickness of bond wafer and base wafer is measured, and combination of bond wafer and base wafer is selected such that difference in thickness between the wafers is less than 5 ?m, and selected bond and base wafers are bonded. This method can inhibit variation in thickness in marble pattern that occurs in thin film and produce bonded wafer including thin film with uniform thickness.Type: ApplicationFiled: May 19, 2014Publication date: April 28, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro KOBAYASHI, Hiroji AGA
-
Publication number: 20160079114Abstract: The present invention provides a method of manufacturing a bonded wafer, including performing RTA under an atmosphere containing hydrogen on a bonded wafer after separating the bond wafer constituting the bonded wafer, and subsequently performing a sacrificial oxidation process to reduce the thickness of the thin film, wherein the RTA is performed under conditions of a retention start temperature of more than 1150° C. and a retention end temperature of 1150° C. or less. The invention can inhibit the BMD density from increasing and sufficiently flatten the surface of a thin film when the thin film of the bonded wafer is flattened and thinned by the combination of the RTA and sacrificial oxidation processes.Type: ApplicationFiled: March 25, 2014Publication date: March 17, 2016Inventors: Toru ISHIZUKA, Norihiro KOBAYASHI
-
Patent number: 9240344Abstract: A method for manufacturing a SOI wafer, including a step of performing a thickness reducing adjustment to a SOI layer of the SOI wafer by carrying out a sacrificial oxidation to the SOI wafer for effecting thermal oxidation to a surface of the SOI layer and removing a formed thermal oxide film, wherein, when the thermal oxidation in the sacrificial oxidation treatment is carried out with the use of a batch processing heat treatment furnace during the rising of a temperature and/or the falling of a temperature, a substantially concentric oxide film thickness distribution is formed on the surface of the SOI layer. The result is a method for manufacturing a SOI wafer that enables manufacturing a SOI wafer that has improved radial film thickness distribution with good productivity by performing the sacrificial oxidation treatment for forming a substantially concentric oxide film and removing the formed thermal oxide film.Type: GrantFiled: November 13, 2012Date of Patent: January 19, 2016Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroji Aga, Norihiro Kobayashi
-
Publication number: 20150340279Abstract: The present invention provides a method for manufacturing SOI wafer, wherein, after plasma treatment has been performed on at least one surface of a bonding interface of the bond wafer and a bonding interface of the base wafer, bonding is performed through the oxide film, and the bond wafer is delaminated at the ion implanted layer by the delamination heat treatment comprising a first heat treatment at 250° C. or less for 2 hours or more and a second heat treatment at 400° C. to 450° C. for 30 minutes or more. Thereby, the method of manufacturing the SOI wafer that is small in SOI layer film thickness range, is small in surface roughness of the SOI layer surface, is smooth in shape of a terrace part and has no defects such as voids, blisters and so forth in the SOI layer can be provided.Type: ApplicationFiled: December 10, 2013Publication date: November 26, 2015Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro KOBAYASHI, Isao YOKOKAWA, Hiroji AGA
-
Patent number: 9093497Abstract: The present invention is directed to a method for manufacturing an SOI wafer in which the bonded SOI wafer after the delamination by the ion implantation delamination method is subjected to a rapid thermal oxidation process such that an oxide film is formed on a surface of the SOI layer, the oxide film is removed, the bonded SOI wafer is then subjected to a flattening heat treatment to flatten the surface of the SOI layer, the flattening heat treatment causing migration of silicon atoms of the surface of the SOI layer, and the bonded SOI wafer is then subjected to a sacrificial oxidation process to adjust a film thickness of the SOI layer. The method enables efficient manufacture of a high quality SOI wafer having an SOI layer with sufficiently reduced surface roughness of the SOI layer surface and fewer deep pits in the SOI layer surface.Type: GrantFiled: December 26, 2012Date of Patent: July 28, 2015Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Toru Ishizuka, Hiroji Aga
-
Patent number: 9076840Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100° C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900° C. or more and 1000° C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed.Type: GrantFiled: November 30, 2012Date of Patent: July 7, 2015Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Hiroji Aga, Isao Yokokawa, Toru Ishizuka, Masahiro Kato
-
Publication number: 20150017783Abstract: The present invention is directed to a method for manufacturing an SOI wafer in which the bonded SOI wafer after the delamination by the ion implantation delamination method is subjected to a rapid thermal oxidation process such that an oxide film is formed on a surface of the SOI layer, the oxide film is removed, the bonded SOI wafer is then subjected to a flattening heat treatment to flatten the surface of the SOI layer, the flattening heat treatment causing migration of silicon atoms of the surface of the SOI layer, and the bonded SOI wafer is then subjected to a sacrificial oxidation process to adjust a film thickness of the SOI layer. The method enables efficient manufacture of a high quality SOI wafer having an SOI layer with sufficiently reduced surface roughness of the SOI layer surface and fewer deep pits in the SOI layer surface.Type: ApplicationFiled: December 26, 2012Publication date: January 15, 2015Inventors: Norihiro Kobayashi, Toru Ishizuka, Hiroji Aga
-
Publication number: 20140329372Abstract: A method for manufacturing a SOI wafer, including a step of performing a thickness reducing adjustment to a SOI layer of the SOI wafer by carrying out a sacrificial oxidation to the SOI wafer for effecting thermal oxidation to a surface of the SOI layer and removing a formed thermal oxide film, wherein, when the thermal oxidation in the sacrificial oxidation treatment is carried out with the use of a batch processing heat treatment furnace during the rising of a temperature and/or the falling of a temperature, a substantially concentric oxide film thickness distribution is formed on the surface of the SOI layer. The result is a method for manufacturing a SOI wafer that enables manufacturing a SOI wafer that has improved radial film thickness distribution with good productivity by performing the sacrificial oxidation treatment for forming a substantially concentric oxide film and removing the formed thermal oxide film.Type: ApplicationFiled: November 13, 2012Publication date: November 6, 2014Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Hiroji Aga, Norihiro Kobayashi
-
Publication number: 20140322895Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100° C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900° C. or more and 1000° C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed.Type: ApplicationFiled: November 30, 2012Publication date: October 30, 2014Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Hiroji Aga, Isao Yokokawa, Toru Ishizuka, Masahiro Kato
-
Patent number: 8823130Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.Type: GrantFiled: March 1, 2011Date of Patent: September 2, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
-
Patent number: 8697544Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.Type: GrantFiled: October 14, 2009Date of Patent: April 15, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tohru Ishizuka, Norihiro Kobayashi, Nobuhiko Noto
-
Patent number: 8466538Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.Type: GrantFiled: February 19, 2009Date of Patent: June 18, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
-
Publication number: 20120326268Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.Type: ApplicationFiled: March 1, 2011Publication date: December 27, 2012Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
-
Patent number: 8202787Abstract: A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.Type: GrantFiled: November 11, 2009Date of Patent: June 19, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tohru Ishizuka, Norihiro Kobayashi, Hiroji Aga, Nobuhiko Noto
-
Patent number: 8173521Abstract: The present invention is a method for manufacturing a bonded wafer by an ion implantation delamination method including at least the steps of, bonding a bond wafer having a micro bubble layer formed by gas ion implantation with a base wafer to be a supporting substrate, delaminating the bond wafer along the micro bubble layer as a boundary to form a thin film on the base wafer, the method comprising, cleaning the bonded wafer after delaminating the bond wafer using ozone water; performing rapid thermal anneal process under a hydrogen containing atmosphere; forming a thermal oxide film on a surface layer of the bonded wafer by subjecting to heat treatment under an oxidizing gas atmosphere and removing the thermal oxide film; subjecting to heat treatment under a non-oxidizing gas atmosphere.Type: GrantFiled: July 3, 2008Date of Patent: May 8, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Hiroji Aga, Yasuo Nagaoka, Nobuhiko Noto
-
Patent number: 8097523Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.Type: GrantFiled: February 17, 2009Date of Patent: January 17, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
-
Publication number: 20110271275Abstract: [The present invention] improves the user-friendliness of a software distribution management system that uses representative clients. The computer system according to the present invention comprises a plurality of clients, a server computer that includes software to be distributed to one or more of the plurality of the clients, and a network for coupling the server computer to the plurality of client computers. Based on information from the plurality of clients, the server computer classifies the plurality of clients into a plurality of groups, selects a representative client for each group, and executes distribution of the software to the representative clients. The representative clients that have received the software distribution distribute the software to the other clients belonging to the same group. The server computer outputs management display information to a management screen on the basis of software distribution management information.Type: ApplicationFiled: April 28, 2010Publication date: November 3, 2011Applicant: HITACHI, LTD.Inventors: Hiroyuki Ochi, Mitsunori Satomi, Nobuo Beniyama, Norihiro Kobayashi
-
Publication number: 20110223740Abstract: A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.Type: ApplicationFiled: November 11, 2009Publication date: September 15, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tohru Ishizuka, Norihiro Kobayashi, Hiroji Aga, Nobuhiko Noto
-
Publication number: 20110212598Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.Type: ApplicationFiled: October 14, 2009Publication date: September 1, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tohru Ishizuka, Norihiro Kobayashi, Nobuhiko Noto