Abstract: Arsenic is diffused previously on a most outside surface of a n.sup.- -type epitaxial layer (2), and after forming gate oxide films (3) and gate electrodes (4), p-type base regions (8) and n.sup.+ -type source layers (7) are formed in a self-aligned manner with the gate electrodes (4) by a DSA technique and double diffusion. Thereby, a lateral directional junction depth of the p-type base regions (8) is compensated at the most outside surface, and a channel length of channels (9) is shortened substantially. When designing a threshold voltage, an impurity density of the p-type base regions (8) can be set higher than that of the conventional device by an amount corresponding to an impurity density of the arsenic of the most outside surface, and p-type pinch layers (14) formed underneath the n.sup.+ -type source layers (7) of the p-type base regions are (8) are lowered correspondingly in resistance.