Abstract: A drive device protection structure has a rotary electric machine, a gearbox connected the rotary electric machine, an undercover disposed underneath the drive device and a protecting plate provided to the undercover. The rotary electric machine has a rotary electric machine housing that has a rotary electric machine flange. The gearbox has a gearbox housing that has a gearbox flange. The rotary electric machine flange and the gearbox flange are connected together. The rotary electric machine flange and the gearbox flange are formed such that a lower surface of the gearbox flange is positioned lower than a lower surface of the rotary electric machine flange. The protecting plate is formed of a material more rigid than a material of the undercover. The protecting plate is provided beneath connecting part between the rotary electric machine flange and the gearbox flange so as to face the connecting part.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, the semiconductor layer having a first surface and a second surface on an opposite side to the first surface; a plurality of conductive layers extending in a direction from the first surface side toward the second surface side of the semiconductor layer; a first semiconductor region of a second conductivity type surrounding part of each of the plurality of conductive layers on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and an insulating film provided between each of the plurality of conductive layers and the semiconductor layer and between each of the plurality of conductive layers and the first semiconductor region.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, the semiconductor layer having a first surface and a second surface on an opposite side to the first surface; a plurality of conductive layers extending in a direction from the first surface side toward the second surface side of the semiconductor layer; a first semiconductor region of a second conductivity type surrounding part of each of the plurality of conductive layers on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and an insulating film provided between each of the plurality of conductive layers and the semiconductor layer and between each of the plurality of conductive layers and the first semiconductor region.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

Abstract: According to one embodiment, a nonvolatile memory device including MOS transistors formed in a surface of one semiconductor substrate is provided. The device includes a first and second MOS transistors. The first MOS transistor includes a first source and drain regions spaced from each other, a first gate insulating film provided on the surface, a first gate electrode provided on the first gate insulating film, and a first channel region located immediately below the first gate insulating film and containing impurities of both conductivity types. The second MOS transistor includes a second source and drain regions spaced from each other, a second gate insulating film provided on the surface, a second gate electrode provided on the second gate insulating film, and a second channel region located immediately below the second gate insulating film and having an identical concentration profile of the impurity to the first channel region.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises forming a first insulating film on a semiconductor substrate, processing the first insulating film into a predetermined pattern, forming a first gate electrode structure on the first insulating film, the first gate electrode structure having a smaller width than that of the processed first insulating film in a channel length direction, introducing a first impurity of a first conductivity type into the semiconductor substrate via the processed first insulting film using the first gate electrode structure as a mask, and introducing a second impurity of the first conductivity type into the semiconductor substrate using the first gate electrode structure and the first insulating film as a mask.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a first device-isolation insulation film that divides the semiconductor substrate at a first transistor region into first device regions; a second device-isolation insulation film that divides the semiconductor substrate at a second transistor region into second device regions; a plurality of first transistors formed in the first transistor region; a plurality of second transistors formed in the second transistor region; and an anti-inversion diffusion layer formed under the first device-isolation insulation film. Each of the first and second transistors includes, respectively: a first and second gate insulation film provided respectively on the first and second device regions; a first and second gate electrode provided respectively on the first and second gate insulation films; and a first and second diffusion layer formed respectively on a surface of the semiconductor substrate so as to sandwich the first and second gate electrodes.

Abstract: A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n?1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a first element isolation insulating film containing an organic substance which surrounds a first region, a memory cell arranged in the first region, a second element isolation insulating film containing an organic substance which surrounds a second region, a peripheral transistor arranged in the second region, and a first impurity layer which is provided in the semiconductor substrate along a side surface of the second element isolation insulating film.

Abstract: A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n?1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines.

Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.