Patents by Inventor Norihisa Yanagihara
Norihisa Yanagihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9379763Abstract: Provided is a wireless device and a wireless network capable of readily communicating wirelessly using different frequency bands and wireless formats to match the state of wireless communication at the installation location of the facility being monitored. A wireless device for performing wireless communication using a wireless module suited to the state of communication, the wireless device being provided with a plurality of wireless modules on a base substrate, wherein the wireless modules are a plurality of wireless modules between which the frequency and/or the wireless format differ. The wireless device is characterized in being provided with: a device controller for selecting a wireless module suited to the state of communication, the device controller being detachably mounted on the base substrate and connected to the plurality of wireless modules by signal wires; and a terminal block for external connection and a communication interface, which are connected to the device controller.Type: GrantFiled: December 8, 2011Date of Patent: June 28, 2016Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Hajime Kihara, Norihisa Yanagihara, Takashi Iwaki, Takayoshi Fujioka
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Patent number: 9148297Abstract: An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections.Type: GrantFiled: February 18, 2011Date of Patent: September 29, 2015Assignee: HITACHI, LTD.Inventors: Tatsuya Maruyama, Tsutomu Yamada, Norihisa Yanagihara, Shinji Yonemoto, Takashi Iwaki, Hironori Ohashi, Yutaka Matsumoto
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Patent number: 8788735Abstract: An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.Type: GrantFiled: August 20, 2009Date of Patent: July 22, 2014Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Tatsuya Maruyama, Tsutomu Yamada, Norihisa Yanagihara, Shinji Yonemoto, Takashi Iwaki, Hiroshi Fujii
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Publication number: 20140036721Abstract: Provided is a wireless device and a wireless network capable of readily communicating wirelessly using different frequency bands and wireless formats to match the state of wireless communication at the installation location of the facility being monitored. A wireless device for performing wireless communication using a wireless module suited to the state of communication, the wireless device being provided with a plurality of wireless modules on a base substrate, wherein the wireless modules are a plurality of wireless modules between which the frequency and/or the wireless format differ. The wireless device is characterized in being provided with: a device controller for selecting a wireless module suited to the state of communication, the device controller being detachably mounted on the base substrate and connected to the plurality of wireless modules by signal wires; and a terminal block for external connection and a communication interface, which are connected to the device controller.Type: ApplicationFiled: December 8, 2011Publication date: February 6, 2014Applicant: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Hajime Kihara, Norihisa Yanagihara, Takashi Iwaki, Takayoshi Fujioka
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Patent number: 8069273Abstract: A processing module to use for a processing system having a plurality of processing modules connected via a communication line is comprising mounting position information for the processing module in the communication line; a unique logical address to indicate the processing module; a database to correspond with a physical address of the processing module in the communication line; a position identification device to identify the mounting position information in the communication line of the processing module; a unique/physical address conversion device to fetch the physical address corresponding to the unique logical address from the database using a data packet having the unique logical address as a destination; and a position/physical address conversion device for searching for the physical address from the mounting position information.Type: GrantFiled: July 24, 2006Date of Patent: November 29, 2011Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Atsushi Ito, Norihisa Yanagihara
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Publication number: 20110205886Abstract: An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections. The network provides a logical ring topology for a packet communication path.Type: ApplicationFiled: February 18, 2011Publication date: August 25, 2011Inventors: Tatsuya Maruyama, Tsutomu Yamada, Norihisa Yanagihara, Shinji Yonemoto, Takashi Iwaki, Hironori Ohashi, Yutaka Matsumoto
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Patent number: 7861115Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.Type: GrantFiled: June 24, 2008Date of Patent: December 28, 2010Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Norihisa Yanagihara, Hajime Kihara, Tsutomu Yamada, Makiko Naemura, Kenji Seino
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Patent number: 7814224Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.Type: GrantFiled: January 24, 2008Date of Patent: October 12, 2010Assignee: Hitachi Industrial Equipment Systems Co.Inventors: Tatsuya Maruyama, Tsutomu Yamada, Hideaki Suzuki, Norihisa Yanagihara, Makiko Naemura
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Patent number: 7716405Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.Type: GrantFiled: November 15, 2006Date of Patent: May 11, 2010Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Tatsuya Maruyama, Atsushi Ito, Fumiyuki Tamura, Norihisa Yanagihara, Makiko Naemura
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Publication number: 20100070668Abstract: An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.Type: ApplicationFiled: August 20, 2009Publication date: March 18, 2010Inventors: Tatsuya Maruyama, Tsutomu Yamada, Norihisa Yanagihara, Shinji Yonemoto, Takashi Iwaki, Hiroshi Fujii
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Publication number: 20090013221Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.Type: ApplicationFiled: June 24, 2008Publication date: January 8, 2009Applicant: Hitachi Industrial Equipment System Co., Ltd.Inventors: Norihisa Yanagihara, Hajime Kihara, Tsutomu Yamada, Makiko Naemura, Kenji Seino
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Publication number: 20080195732Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.Type: ApplicationFiled: January 24, 2008Publication date: August 14, 2008Inventors: Tatsuya Maruyama, Tsutomu Yamada, Hideaki Suzuki, Norihisa Yanagihara, Makiko Naemura
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Publication number: 20070112983Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.Type: ApplicationFiled: November 15, 2006Publication date: May 17, 2007Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Tatsuya Maruyama, Atsushi Ito, Fumiyuki Tamura, Norihisa Yanagihara, Makiko Naemura
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Publication number: 20070038745Abstract: A processing module to use for a processing system having a plurality of processing modules connected via a communication line is comprising mounting position information for the processing module in the communication line; a unique logical address to indicate the processing module; a database to correspond with a physical address of the processing module in the communication line; a position identification device to identify the mounting position information in the communication line of the processing module; a unique/physical address conversion device to fetch the physical address corresponding to the unique logical address from the database using a data packet having the unique logical address as a destination; and a position/physical address conversion device for searching for the physical address from the mounting position information.Type: ApplicationFiled: July 24, 2006Publication date: February 15, 2007Inventors: Tsutomu Yamada, Hiromichi Endoh, Noritaka Matsumoto, Satoru Funaki, Atsushi Ito, Norihisa Yanagihara
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Publication number: 20040201519Abstract: A positioning system offers positioning information on the basis of a signal transmitted from a quasi-zenith satellite. Multiple reference stations disposed on the ground receive signals from a plurality of positioning satellites. A communication station corrects the signals the reference stations have received, and transmits them to the quasi-zenith satellite. A positioning information offering apparatus transmits the signal received from the quasi-zenith satellite and a positional information to a positioning apparatus.Type: ApplicationFiled: April 9, 2004Publication date: October 14, 2004Inventors: Toshiyuki Aoki, Norihisa Yanagihara, Satoshi Sugawara, Toshihide Maeda, Kenjiro Fujii, Masahiko Watanabe
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Patent number: 6785204Abstract: An actuator control device is provided for performing some modifications such as making the output of a disturbance observer zero for quickly restoring the proper tracking control if the out-of-track state takes place and if the outside force exceeding the maximum force generated by an actuator is applied to the device itself. In the actuator control device, a disturbance observer estimates disturbance added to the actuator. The second control signal corresponding to the estimated disturbance is added to the first control signal. The added signal is made to be a third control signal. Further, the second control signal is stored in a storage unit. The stored value is further added to the third control signal as the fifth control signal. By performing some modifications such as making the second control signal zero according to the abnormal state, this arrangement makes it possible to quickly restore the proper tracking control even if the out-of-track state takes place.Type: GrantFiled: August 24, 2000Date of Patent: August 31, 2004Assignee: Hitachi, Ltd.Inventors: Atsushi Okuyama, Shinya Imura, Masato Soma, Norihisa Yanagihara
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Publication number: 20040116134Abstract: In a mobile communication using satellites, the present invention allows a mobile to receive a service wherever it is. To do so, when positioning the current location of a mobile using a satellite that sends the GPS signal, the mobile receives an electric wave directly from the satellite for performing positioning when the electric wave can be received directly from the satellite. On the other hand, when an electric wave cannot be received directly from the satellite, the mobile receives an electric wave from a pseudo-satellite or performs positioning using a wireless network between other mobiles and the mobile. Positioning may also be performed using an indoor wireless network.Type: ApplicationFiled: November 4, 2003Publication date: June 17, 2004Inventors: Toshihide Maeda, Kazunori Takahashi, Norihisa Yanagihara, Naomichi Nonaka, Hideya Suzuki, Tsutomu Noda, Hitoshi Yamadera
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Patent number: 5720442Abstract: A load torque imposed on a take-up reel motor is estimated from the current in a take-up reel motor and the rotational speed of the take-up reel. The current value supplied to the take-up reel motor is adjusted on the basis of the estimated load torque. A tape feed rate detected is compared with a reference signal produced from a target tape speed signal. On the basis of the comparison result, the torque of the take-up reel motor is controlled in such a manner that the tape feed rate assumes a predetermined value. The gain of a speed control system for controlling the rotational speed of the take-up reel is adjusted on the basis of a detected period of tape speed.Type: GrantFiled: July 16, 1996Date of Patent: February 24, 1998Assignee: Hitachi, Ltd.Inventors: Norihisa Yanagihara, Shinsuke Nakagawa, Shigeyuki Kobata, Masao Iwakura, Kazuo Sakai
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Patent number: 5039027Abstract: This invention relates to tape tension control in a device which has a capstan disposed between a supply reel and which transport a tape wound around the supply reel to the take-up reel. While the tape, mounted on the reels, is running, the tape speed is varied greatly, and during this speed change period, a tape tension variation between the supply reel and the capstan and a tape tension variation between the capstan and the take-up reel are found. From those tape tension variations, ratios of moments of inertia of the reels with the tape thereon to the tape radii are found, and according to the values of the ratios, the gains of the loops of the tension control system is adjusted.Type: GrantFiled: November 1, 1989Date of Patent: August 13, 1991Assignee: Hitachi, Ltd.Inventors: Norihisa Yanagihara, Katsuo Ooki, Takao Terayama, Masanori Arahori