Patents by Inventor Norihito Nakamura

Norihito Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power converter apparatus with a circuit for preventing destruction of a power device
    Patent number: 6661681
    Abstract: A power converter apparatus comprises a detection circuit, a control circuit and a time period generating circuit. The detection circuit detects whether a power device is in a short-circuit state. The control circuit sets, when the detection circuit has detected that the power device is in the short-circuit state, the power device in an inoperable state for a predetermined time period, and restores the power device to an operable state after the passing of the predetermined time period. The time period generating circuit defines the predetermined time period for setting the power device in the inoperable state, by measuring a time from the detection of the short-circuit state by the detection circuit.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: December 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Norihito Nakamura
  • Power converter apparatus using power device
    Publication number: 20020163820
    Abstract: A power converter apparatus comprises a detection circuit, a control circuit and a time period generating circuit. The detection circuit detects whether a power device is in a short-circuit state. The control circuit sets, when the detection circuit has detected that the power device is in the short-circuit state, the power device in an inoperable state for a predetermined time period, and restores the power device to an operable state after the passing of the predetermined time period. The time period generating circuit defines the predetermined time period for setting the power device in the inoperable state, by measuring a time from the detection of the short-circuit state by the detection circuit.
    Type: Application
    Filed: May 3, 2002
    Publication date: November 7, 2002
    Inventor: Norihito Nakamura
  • Semiconductor chip
    Patent number: 6069401
    Abstract: A system and method for forming semiconductor devices on more than one surface of a chip is disclosed. A bed is formed with separate portions which connect to a first circuit on a first semiconductor face of a semiconductor chip. A second circuit resides on the opposite face of the semiconductor chip. Providing two circuits on separate faces of a semiconductor chip allows for savings of physical area of the chip. By providing a face-to-face contact with a first circuit, heat generated by the first circuit may be drawn away by the bed. Accordingly, smaller semiconductor chips may be realized without excessive heat generation.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norihito Nakamura, Yukihide Nakamoto