Patents by Inventor Noriko Yabumoto

Noriko Yabumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for logic equivalence verification, and computer product
    Patent number: 7971165
    Abstract: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Noriko Yabumoto, Akiko Satoh, Zhengjun Zhang, Takashi Matsuura
  • Method and apparatus for logic equivalence verification, and computer product
    Publication number: 20080256498
    Abstract: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 16, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Noriko Yabumoto, Akiko Satoh, Zhengjun Zhang, Takashi Matsuura