Patents by Inventor Norimitsu Hayakawa
Norimitsu Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10942815Abstract: A storage control system to provide file-level storage and block-level storage services. The storage control system has a computer system including a second I/O unit configured to receive block-level storage related requests, a processor unit, a first memory unit, and a storage unit; and a programmable logic device including a first I/O unit configured to receive file-level storage related requests, an interface unit configured to communicate with the computer system, one or more programmable hardware-implemented processing units and for processing of file-level storage related requests, and a second memory unit.Type: GrantFiled: July 9, 2015Date of Patent: March 9, 2021Assignees: HITACHI, LTD., HITACHI VANTARA LLCInventors: Sathisha Poojary, Christopher James Aston, Graham Ellement, Simon Carl Johnson, Hiroyuki Mitome, Naoki Inoue, Norimitsu Hayakawa, Yukari Hatta, Yasuo Hirata, Ryosuke Matsubara
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Patent number: 10289564Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.Type: GrantFiled: July 8, 2015Date of Patent: May 14, 2019Assignee: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Takao Totsuka, Toshiomi Moriki, Satoshi Kinugawa
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Publication number: 20180203805Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.Type: ApplicationFiled: July 8, 2015Publication date: July 19, 2018Applicant: HITACHI, LTD.Inventors: Yukari HATTA, Norimitsu HAYAKAWA, Takao TOTSUKA, Toshiomi MORIKI, Satoshi KINUGAWA
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Patent number: 9977740Abstract: A computer, on which a plurality of operating systems run, wherein the plurality of operating systems includes a first operating system and a second operating system configured to generate a plurality of virtual computers. The first operating system runs on a first logical resource, and the second operating system runs on a second logical resource. A third operating system runs on each of the plurality of virtual computers. The third operating system secures a cache memory area in a virtual memory. The second operating system generates location information, which indicates a location of the cache memory area in a physical address space that the second operating system manages. The first operating system obtain data stored in the cache memory area based on the location information.Type: GrantFiled: March 7, 2014Date of Patent: May 22, 2018Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Masatoshi Konagaya, Takao Totsuka, Yukari Hatta
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Publication number: 20180137013Abstract: A storage control system to provide file-level storage and block-level storage services. The storage control system has a computer system including a second 1/0 unit configured to receive block-level storage related requests, a processor unit, a first memory unit, and a storage unit; and a programmable logic device including a first 1/0 unit configured to receive file-level storage related requests, an interface unit configured to communicate with the computer system, one or more programmable hardware-implemented processing units and for processing of file-level storage related requests, and a second memory unit.Type: ApplicationFiled: July 9, 2015Publication date: May 17, 2018Inventors: Sathisha POOJARY, Christopher James ASTON, Graham ELLEMENT, Simon Carl JOHNSON, Hiroyuki MITOME, Naoki INOUE, Norimitsu HAYAKAWA, Yukari HATTA, Yasuo HIRATA, Ryosuke MATSUBARA
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Publication number: 20170004081Abstract: A computer, on which a plurality of operating systems run, wherein the plurality of operating systems includes a first operating system and a second operating system configured to generate a plurality of virtual computers. The first operating system runs on a first logical resource, and the second operating system runs on a second logical resource. A third operating system runs on each of the plurality of virtual computers. The third operating system secures a cache memory area in a virtual memory. The second operating system generates location information, which indicates a location of the cache memory area in a physical address space that the second operating system manages. The first operating system obtain data stored in the cache memory area based on the location information.Type: ApplicationFiled: March 7, 2014Publication date: January 5, 2017Inventors: Norimitsu HAYAKAWA, Masatoshi KONAGAYA, Takao TOTSUKA, Yukari HATTA
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Patent number: 9361124Abstract: A computer system comprising a plurality of computers on which a plurality of operating systems run, wherein a memory stores a first hardware control unit, wherein a storage device stores a first OS image, a second OS image, a second hardware control unit for executing start processing of the second OS, and an address rewrite unit, wherein the second hardware control unit includes a start unit for starting the second hardware control unit, wherein the address rewrite unit which is started by the first OS is configured to: obtain an address of a storage area, in which address data to be rewritten is stored, as a target address, rewrite the address data stored in the storage area corresponding to the obtained target address and start the start unit, wherein the start unit is configured to start the second hardware control unit by using the rewritten address data.Type: GrantFiled: April 24, 2014Date of Patent: June 7, 2016Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Keisuke Yoshida, Takashi Shimojo, Masatoshi Konagaya, Yoshihito Nakagawa, Toshiomi Moriki
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Patent number: 9323566Abstract: The network connection of a VM (target VM) that has been live-migrated from a first physical computer to a second physical computer is restored in a virtual computer system in which communication is performed using a certain type of information outside the jurisdiction of a virtualization mechanism. When receiving a packet from the VM, the first virtualization mechanism of the first physical computer extracts a certain type of information from the packet and registers the extracted certain type of information in a first management information unit. The first virtualization mechanism transmits the certain type of information in the first management information unit to the second virtualization mechanism of the second physical computer during live migration.Type: GrantFiled: August 22, 2012Date of Patent: April 26, 2016Assignee: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Hiroshi Miki, Shiro Nohara, Takao Totsuka
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Patent number: 9134915Abstract: A hypervisor as a movement source stores key information, and the key information is registered in a storage using the stored key information through a logical HBA which is used for migration.Type: GrantFiled: August 1, 2013Date of Patent: September 15, 2015Assignee: HITACHI, LTD.Inventors: Norimitsu Hayakawa, Eiichiro Oiwa, Yukari Hatta, Hiroshi Miki, Takuji Teraya
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Patent number: 9038067Abstract: A live migration in a virtual computer system. On a source physical computer, the control information area of the source logical FC-HBA (managed by an OS) is copied to the control information area of a dummy logical FC-HBA managed by a hypervisor. After an FC login to the dummy FC-HBA, an address conversion table is rewritten so that a host physical address for referring to the control information area of a logical HBA1? can be referred to using a guest logical address for referring to the control information area of the source FC-HBA. After the FC logout of the source FC-HBA, using a WWN of the FC used for the FC logout, a login to the destination logic FC-HBA is performed. Next, the OS on the source computer is taken over by the destination computer. Therefore, the disk accessed on the source computer can be accessed from the destination FC-HBA.Type: GrantFiled: October 24, 2012Date of Patent: May 19, 2015Assignee: Hitachi, Ltd.Inventors: Hiroshi Miki, Eiichiro Oiwa, Yukari Hatta, Norimitsu Hayakawa, Takuji Teraya
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Publication number: 20150121372Abstract: The network connection of a VM (target VM) that has been live-migrated from a first physical computer to a second physical computer is restored in a virtual computer system in which communication is performed using a certain type of information outside the jurisdiction of a virtualization mechanism. When receiving a packet from the VM, the first virtualization mechanism of the first physical computer extracts a certain type of information from the packet and registers the extracted certain type of information in a first management information unit. The first virtualization mechanism transmits the certain type of information in the first management information unit to the second virtualization mechanism of the second physical computer during live migration.Type: ApplicationFiled: August 22, 2012Publication date: April 30, 2015Applicant: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Hiroshi Miki, Shiro Nohara, Takao Totsuka
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Publication number: 20140372742Abstract: A computer system comprising a plurality of computers on which a plurality of operating systems run, wherein a memory stores a first hardware control unit, wherein a storage device stores a first OS image, a second OS image, a second hardware control unit for executing start processing of the second OS, and an address rewrite unit, wherein the second hardware control unit includes a start unit for starting the second hardware control unit, wherein the address rewrite unit which is started by the first OS is configured to: obtain an address of a storage area, in which address data to be rewritten is stored, as a target address, rewrite the address data stored in the storage area corresponding to the obtained target address and start the start unit, wherein the start unit is configured to start the second hardware control unit by using the rewritten address data.Type: ApplicationFiled: April 24, 2014Publication date: December 18, 2014Applicant: Hitachi, Ltd.Inventors: NORIMITSU HAYAKAWA, Keisuke Yoshida, Takashi Shimojo, Masatoshi Konagaya, Yoshihito Nakagawa, Toshiomi Moriki
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Publication number: 20140059302Abstract: A hypervisor as a movement source stores key information, and the key information is registered in a storage using the stored key information through a logical HBA which is used for migration.Type: ApplicationFiled: August 1, 2013Publication date: February 27, 2014Applicant: HITACHI, LTD.Inventors: Norimitsu HAYAKAWA, Eiichiro OIWA, Yukari HATTA, Hiroshi MIKI, Takuji TERAYA
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Patent number: 8479198Abstract: A hypervisor sets all physical areas in an allocation area, which is allocated to a virtual machine from within a physical memory and is configured from a plurality of physical areas, to a write protect mode. In a case where a physical processor identifies that the write-destination area from the virtual machine is in the write protect mode, the hypervisor manages the write-destination area as an updated area, and cancels the write protect mode of the write-destination area. At a certain point in time, the hypervisor copies data inside the updated physical area from within the allocation area to a storage area (a copy area) that differs from the allocation area. In a case where a prescribed failure is detected in the physical area, the hypervisor restores data from the copy area.Type: GrantFiled: February 8, 2011Date of Patent: July 2, 2013Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Takao Totsuka
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Patent number: 8316365Abstract: In scheduling shared processing that has a higher priority than LPAR processing, giving precedence to physical CPUs running idle LPARs prevents prolonged hold-up of LPAR processing. In a system is comprised of multiple physical CPUs, multiple LPARs to which these physical CPUs are allocated and which execute programs under their guest OSes, and a management program managing these LPARs, a few additional units are introduced: a guest OS monitoring unit that can grasp the states of guest OSes running on these LPARs and a dispatcher unit that allocates one of these physical CPUs to shared processing requested by the management program, which has a higher priority than LPAR processing. When a request for shared processing arises, the dispatcher unit interrogates the guest OS monitoring unit and, based on the information obtained from it, gives priority of allocation to the physical CPU processing an idle LPAR.Type: GrantFiled: September 23, 2011Date of Patent: November 20, 2012Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Shuhei Matsumoto
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Patent number: 8112750Abstract: In scheduling shared processing that has a higher priority than LPAR processing, giving precedence to physical CPUs running idle LPARs prevents prolonged hold-up of LPAR processing. In a system is comprised of multiple physical CPUs, multiple LPARs to which these physical CPUs are allocated and which execute programs under their guest OSes, and a management program managing these LPARs, a few additional units are introduced: a guest OS monitoring unit that can grasp the states of guest OSes running on these LPARs and a dispatcher unit that allocates one of these physical CPUs to shared processing requested by the management program, which has a higher priority than LPAR processing. When a request for shared processing arises, the dispatcher unit interrogates the guest OS monitoring unit and, based on the information obtained from it, gives priority of allocation to the physical CPU processing an idle LPAR.Type: GrantFiled: January 25, 2008Date of Patent: February 7, 2012Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Shuhei Matsumoto
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Publication number: 20120030675Abstract: In scheduling shared processing that has a higher priority than LPAR processing, giving precedence to physical CPUs running idle LPARs prevents prolonged hold-up of LPAR processing. In a system is comprised of multiple physical CPUs, multiple LPARs to which these physical CPUs are allocated and which execute programs under their guest OSes, and a management program managing these LPARs, a few additional units are introduced: a guest OS monitoring unit that can grasp the states of guest OSes running on these LPARs and a dispatcher unit that allocates one of these physical CPUs to shared processing requested by the management program, which has a higher priority than LPAR processing. When a request for shared processing arises, the dispatcher unit interrogates the guest OS monitoring unit and, based on the information obtained from it, gives priority of allocation to the physical CPU processing an idle LPAR.Type: ApplicationFiled: September 23, 2011Publication date: February 2, 2012Applicant: HITACHI, LTD.Inventors: Norimitsu HAYAKAWA, Shuhei MATSUMOTO
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Publication number: 20110202919Abstract: A hypervisor sets all physical areas in an allocation area, which is allocated to a virtual machine from within a physical memory and is configured from a plurality of physical areas, to a write protect mode. In a case where a physical processor identifies that the write-destination area from the virtual machine is in the write protect mode, the hypervisor manages the write-destination area as an updated area, and cancels the write protect mode of the write-destination area. At a certain point in time, the hypervisor copies data inside the updated physical area from within the allocation area to a storage area (a copy area) that differs from the allocation area. In a case where a prescribed failure is detected in the physical area, the hypervisor restores data from the copy area.Type: ApplicationFiled: February 8, 2011Publication date: August 18, 2011Inventors: NORIMITSU HAYAKAWA, Takao Totsuka
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Publication number: 20100262741Abstract: A method for making it possible for a virtualization software (VMM) to generally identify a PCI function of an interrupt requester presupposing the existing I/O devices based on the PCI express is provided. An interrupt relay circuit is provided between an I/O device based on the PCI express and a PCI express bridge. The interrupt relay circuit receives and relays an interrupt transaction issued by the I/O device, and records whether there is an interrupt request in an interrupt indicator in association with an interrupt identifier. A VMM 114 uniquely identifies an I/O device of interrupt requester by referring to the interrupt indicator 134.Type: ApplicationFiled: April 12, 2010Publication date: October 14, 2010Inventors: Norimitsu HAYAKAWA, Toshiomi Moriki, Yuji Tsushima, Naoya Hattori
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Publication number: 20090158004Abstract: A TLB virtualization method of a machine virtualization device which, in the case where a TLB is shadowed in a virtualization environment, avoids TLB entry conflicts and is capable of improving the performance of a virtualization environment; wherein a hypervisor is executed on a real machine, an OS is operated on a plurality of virtual machines generated by means of processing based on the hypervisor, TLB entry calculations are carried out using RID values in the virtual machines by means of hypervisor processing, the RID values in the virtual machines used in the TLB entry calculations in the real machine are translated into different values in said plurality of virtual machines, and, further, the values of the bit strings of translated RID values are modified.Type: ApplicationFiled: November 26, 2008Publication date: June 18, 2009Inventors: Tomohide Hasegawa, Makiko Shinohara, Norimitsu Hayakawa, Souichi Takashige