Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to a combination of an FM modulator and FM demodulator to provide a delay circuit for an analog circuit.

Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit, The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including a FM modulator or FM demodulator. The signal delay device will assure undistorted signals.

Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

Abstract: A PWM circuit for generating a PWM wave which is pulse-width modulated in response to binary information and is used for a signal such as a motor driving signal in an R-DAT (rotary head type digital audio tape recorder) comprises a circuit for dividing binary information such as a motor speed error signal provided for generating a PWM wave into plural bit groups and generates PWM waves corresponding to numerical values of these plural bit groups, and a circuit for weighting the generated PWM waves in an analog manner at a ratio corresponding to orders of the respective bit groups and adding the weighted PWM waves. Since binary information is divided into plural bit groups, the bit number of each bit group is small so that the period of PWM wave can be shortened without reducing the quantization bit number of the binary information or shortening reference clock period whereby accuracy of an error signal can be improved when the invention is applied to, e.g., a motor drive device.

Abstract: A CMOS integrated circuit for signal delay comprises CMOS gate circuits connected in multiple stages which deliver out an input binary signal after delaying it by a predetermined delay time. The CMOS gate circuits are arranged in a folded pattern on an integrated circuit substrate and each row of the folded pattern including a part of the CMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists of an N channel element and a P channel element cascade-connected to each other and gate patterns of the respective channels have their width and length adjusted in such a manner that value of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.

Abstract: A disc rotation control device for a compact disc player comprises a stable rotation detection circuit for detecting whether rotation of a compact disc is in a stable state or in an unstable state, a phase control loop for phase-controlling the disc rotation and direct control means for directly controlling the disc rotation. The disc rotation is controlled by the phase control loop when the disc rotation is in a stable state and, if the disc rotation has become unstable, the control of the disc rotation is switched to one by the direct control means. During the phase control, even if an EFM signal reproduced from a disc has become unavailable for some reason, preceding phase difference data is held and used for the disc rotation control.

Abstract: There is provided a data processing circuit for processing symbol data read from a disc of a digital audio system such as a DAD player. Each of the symbol data read from the disc is first stored into a buffer register and then transferred therefrom to a symbol memory in accordance with internal pulse signals, and the number of the pulse signals generated during a period required to process one frame of symbol data is greater than that of symbol data contained in one frame of symbol data. An address data for addressing a desired area of the symbol memory is formed by adding a reference address data generated by counting the internal frame synchronization signals to a relative address data generated by adding together a specific pair of addressing data read out from an address memory, the address memory storing a plurality of groups of addressing data to be used in accordance with each mode of operation of this circuit.

Abstract: In picking up recorded data from a revolving optical disc by an optical reproduction system in an optical type disc reproduction device and detecting time data of Q subcode from the picked up data for performing operations such as searching a target position, the position control device according to this invention facilitates handling of data in cases such as computing time difference by converting detected present time data from a BCD code into a binary code by a BCD/binary conversion circuit and using the binary coded data. For searching a target position, time difference is detected by a time difference detection circuit on the basis of a difference between the binary coded present time data and target time data and a relative position of the optical reproduction system with respect to the optical disc is changed by a relative position change driver such that the time difference is reduced to zero.

Abstract: A subcode signal reading circuit in a compact disc player of the compact disc digital audio system comprises an EFM demodulation circuit which receives an EFM reproduction signal reproduced from a disc, EFM-demodulates the EFM reproduction signal and outputs a demodulated eight-bit signal, a first register in which a Q subcode included in the demodulated eight-bit signal provided by the EFM demodulation circuit is written in eight-bit fashion, a second register to which contents of the first register are transmitted and an error detection circuit for detecting whether or not the Q subcode produced by the EFM demodulation circuit contains error. Transmission of the contents of the first register to the second register is controlled by an output of the error detection circuit in such a manner that the transmission is made when no error has been detected by the error detection circuit. An output of the second register is used in the disc player as a correct Q subcode to be read.

Abstract: In a digital system, there is provided a circuit for detecting and correcting errors in a group of data using Reed-Solomon codes. The group of data is first stored in a memory, and syndromes of the data are produced by a syndrome calculation circuit and fed to an internal data bus. A first data conversion circuit converts the syndromes on the internal data bus into logarithmic values and a multiplier-divider circuit executes multiplication or division of the data on the internal data bus by addition and subtraction operations of the logarithmic values. A second data conversion circuit converts antilogarithmically data from the multiplier-divider circuit, and an addition and subtraction circuit executes addition or subtraction of the data from the second data conversion circuit.

Abstract: There is provided a counter circuit operable in synchronism with a frame of a digital data signal of a digital audio system even if a frame synchronization signal is not detected. The counter circuit comprises a detection circuit for detecting the frame synchronization signal of the digital data signal to produce a frame synchronization detection signal. A series of counters repeatedly count clock pulses reproduced from the digital data signal to produce a count signal when the count of the series of counters reaches a value corresponding to the number of channel bits includes in one (1) frame of the digital data signal. A reproduction frame sychronization signal is generated in response to the frame synchronization signal when the count of the series of counters is within a predetermined range, the reproduction frame synchronization signal resetting the counters.

Abstract: A simplified clock-signal reproducing circuit for reproducing a clock signal from a repetitive pulse signal or a digital signal such as an EFM signal read from a compact disc as a data recording medium of the compact disc digital audio system is provided. A voltage-controlled oscillator generates a first repetition signal, and a second repetition signal is formed from the first repetition signal, the second repetition signal being the clock signal. The repetitive pulse signal is latched by a first latch in response to the clock signal, and a signal which is a delayed output of the first latch is latched by a second latch in response to the clock signal. A voltage representing a phase difference between a clock signal in the repetitive pulse signal and the clock signal generated by the voltage-controlled oscillator is generated in accordance with a first phase difference between the input and output signals of the first latch and a second phase difference between input and output signals of the second latch.

Abstract: A digital signal processing device is disclosed. At an intermediate time point between respective sample data of a digital signal input is interpolated data expressed by the formula ##EQU1## wherein R.sub.l, m and n are positive integers. The digital signal interpolated with this interpolation data d is applied to a digital-to-analog converter where it is converted to an analog signal. This interpolation serves as a low-pass filter for removing unnecessary harmonic components, with the result that a analog filter used in a posterior stage after the digital-to-analog converter requires no steep characteristics and hence can be of a remarkedly simple structure and be manufactured at reduced cost.

Abstract: Analog output signals of a key touch sensor and tonal effect setting manual operators are respectively time division multiplexed and thereafter are converted to digital signals by using an analog to digital converter on a time shared basis. The key touch sensor capable of detecting a key touch of a depressed key can also be used for obtaining an initial touch detection signal by additionally providing a device for holding a peak value of an output signal of the sensor at the beginning of depression of the key. Control factors of various tonal effects are controlled in response to these converted digital signals. Control factors of an attack pitch control effect are controlled in response to the key touch. In imparting a delay vibrato effect, the attack pitch control is automatically applied before the delay vibrato is initiated. In imparting a vibrato effect, the attack pitch control is automatically applied and the vibrato is applied thereafter if a key has been depressed in a staccato form.

Abstract: An electronic musical instrument comprises means for detecting depressed-keys on a keyboard to generate key informations corresponding to said depressed keys, and means for generating a musical tone signal which varies pitch from the pitch of a musical tone generated by a firstly-depressed key to the pitch of a musical tone generated by a secondly-depressed key, in accordance with a key information of said firstly-depressed key and a key information of said secondly-depressed key. In the instrument, means is provided for generating an amplitude coefficient which sequentialy varies from an amplitude of the musical tone generated by the firstly-depressed key to an amplitude of the musical tone generated by the secondly-depressed key whereby the amplitude of said musical tone signal is controlled according to said amplitude coefficient.

Abstract: A groove-end detecting apparatus of a record disk or video disk, arranged to have a pulse generator for generating a pulse of a short period when the movement speed of the pickup arm is great, and having a long period when this movement speed is low, i.e. a pulse having a period inversely proportional to the movement speed of the pickup arm. This pulse is provided as a set pulse to a counter circuit assigned for counting a certain frequency clock pulse so as to generate a groove-end detection signal when the cycle is within the time which is required for the counting of a predetermined value of the count of the clock pulse.

Abstract: An electronic musical instrument having an automatic performance device includes a memory storing in addition to automatic performance data, envelope control data for controlling envelopes of automatic performance tones to be generated. The envelope control data has two logical values and is used for controlling the envelope of the tone at the decaying portion. The value "0" designates a gradual decay and the value "1" designates a quick decay. The automatic performance tones are respectively imparted with either of the gradual and the quick decay shapes suitable for the time intervals between the generated tones in the designated automatic performance pattern.

Abstract: A channel processor capable of assigning a key code provided by a key coder and representing making (or breaking) of a key switch to one of a plurality of channels for storage therein and subsequently detecting breaking (or making) of the same key switch on the side of the channel processor. The assignment of the key code is implemented by holding the key code provided by the key coder during a predetermined period of time, detecting whether conditions for the key code assignment have been satisfied or not in a former half of the holding period and, if such conditions have been satisfied, causing the key code to be stored in an empty channel of a main memory device in a latter half of the holding period. Detection of breaking of the made key switch (or vice versa) is made by once clearing a memory storing the assigned channels by means of a start code generated by the key coder and subsequently finding that a channel among the cleared channels is not stored in the memory again, i.e.

Abstract: A device for detecting a key switch operation capable of detecting an operating state of a plurality of key switches which are commonly connected with respect to each row line (block line) at one terminal thereof and commonly connected with respect to each column line at the other terminal thereof, thereby constituting a switch matrix. If a signal is provided on all column lines, the signal is transmitted to a block line through a key switch which is in operation and thereby a block including the key switch in operation is detected. A signal is then supplied from the detected block line to a column line only through the key switch in operation in the detected block. The position of the key switch in operation is known by detecting the columnn line on which the signal arrives. According to an embodiment of the invention, capacitance elements are provided both on the block lines and on the column lines for effecting delivery of the signal by charging and discharging of these capacitance elements.