Abstract: This invention provides a delay circuit capable of electrically varying the delay amount comprising a first transistor for receiving a signal to be delayed from the base connected to an input terminal and outputting a positive phase signal and a negative phase signal with respect to the signal from the input terminal, respectively from the emitter and the collector thereof; two variable capacity diodes with their terminals of the same polarity connected together and a specified control voltage applied to the point of said connection, one end of the connected diodes being connected to the emitter of said first transistor; a second transistor with the base grounded, the emitter connected to the collector of the above-mentioned first transistor, and the collector connected to one end of a specified resistance; and a delayed signal output terminal having connected thereto the other end of the two variable capacity diodes and the other end of the specified resistance.

Abstract: An input circuit in which an input impedance of a reception amplifier connected to a piezoelectric transducer is selected to be lower than an impedance composed of an inter-electrode capacitance of the piezoelectric transducer, an equivalent capacitance of a cable used to connect the piezoelectric transducer to the reception amplifier, etc., that is, the parallel impedance of those elements connected in parallel to the reception amplifier so that the reception amplifier is used as an amplifier of the current detection type.

Abstract: A sequence program inputting device in a programmable sequence controller includes a separate producing circuit for producing a ladder diagram to be displayed on a display screen and a separate converting circuit for converting the ladder diagram to a machine instruction sequence of the programmable sequence controller to enable independent operations of those circuits.

Abstract: A method for recording and reproducing information characterized in that an information train in which synchronizing signals are arrayed at equal time intervals between information signals is recorded in an information track on a recording medium which is wobbled in synchronism with the synchronizing signals and at a frequency integral times the frequency of the synchronizing signals, that the information train recorded in the information track is read out by read-out means, and that a position of the read-out means is controlled on the basis of the information train read out. The wobbling waveform is 90.degree. out of phase with a harmonic component of the synchronizing signals.

Abstract: A tablet comprising conversion means to convert component forces at three fulcra of an external force applied to one point on a faceplate into electric signals, sensing means to sense that no external force is applied, memory means to store the output signals of the conversion means at the respective fulcra as offset values at, at least, one point of time in the period in which no external force is applied, control means to control so as to execute writing into the memory means upon receiving an output of the sensing means, subtraction means to subtract outputs of the memory means from the outputs of the conversion means at the respective fulcra, and calculation means to execute calculations for evaluating coordinates of the point to which the external force has been applied, from outputs of the subtraction means in accordance with the output of the sensing means.

Abstract: A digital-to-analog conversion system includes a digital-to-analog converter, a source of at least one set of digital input signals and a signal for error compensation and a digital signal for error detection to the converter, a switch to selectively couple either the one set of digital input signals and the signal for error compensation or the signal for error detection to the converter, a clock to generate a switching signal having a predetermined period and duration which is coupled to control the switch, a distribution switch for selectively coupling the output of the digital-to-analog converter to two different terminals, receiving a control input from the clock, a sample and hold circuit to sample and hold the output of the digital-to-analog converter, a detector for detecting a linearity error in the digital-to-analog converter output signal when the digital signal for error detection is coupled as an input thereto, a memory for storing the output of the detector, a circuit to write the output of the d

Abstract: In a digital-to-analog converter having means to convert a digital input signal into an analog signal, processing means to evaluate an error attendant upon the conversion, and memory means to store the evaluated error; a digital-to-analog converter with a compensating circuit wherein the processing means comprises a ramp voltage generator, a clock pulse generator, and counting means to count clock pulses of the generator and to deliver the error on the basis of the count value of the clock pulses at each time when the ramp voltage exceeds the output of the conversion means.

Abstract: A high-speed low-drift operational amplifier is disclosed in which a coefficient circuit having a voltage gain of more than 1 is formed employing a low frequency operational amplifier with a low-drift characteristic to multiply an input voltage by the voltage gain, the coefficient circuit and a low pass filter are connected in cascade to form a drift compensating circuit, and the inverting and non-inverting input terminals of a wide-band operational amplifier are connected to the input and output terminals of the drift compensating circuit, respectively.

Abstract: When error detection codes are added to a sampled signal word which is a digital version of audio information and a control signal which is a digital version of system control information to construct a data frame and a control signal frame, respectively, the error detection code for the data frame is generated under an arithmetic condition different from that for the control signal frame. In this manner, frame identification information is superimposed on the error detection codes. In a reproducing unit, the error detection codes containing the identification information are used to check an error in the reproduced sampled signal word and control signal and to effect the discrimination between the data frame and the control signal frame.

Abstract: An electron beam deflection control system includes a first signal generation circuit which generates a triangular signal varying at a comparatively low speed, a second signal generation circuit which generates a stepped signal varying at a comparatively high speed, and a switching arrangement to change over the first and second signal generation circuits and to drive one of them, whereby the signal from the generation circuit selected by the switching arrangement is used as a deflection signal for an electron beam.

Abstract: An analog comparator comprising a generator circuit which generates an input signal voltage having a certain slew rate, a setting circuit which sets a target or desired voltage, another setting circuit which sets a threshold voltage corresponding to the slew rate of the input signal voltage and an ambient temperature, and a comparison circuit which receives the input signal voltage, the target voltage and the threshold voltage and which delivers a coincidence timing signal upon detecting that the input signal voltage has reached a voltage shifting by the threshold voltage from the target voltage.

Abstract: A control apparatus having an electronic timer including a plurality of flip-flop circuits connected in multiple stages in cascade. Outputs are taken from different stages of the electronic timer and the separate outputs are utilized to produce individual control timing signals which serve for controlling at least one device in accordance with the timing specific to the individual control timing signals.

Abstract: A digital differential analyzer comprises an arithmetic unit for performing an integration operation, a control unit for controlling the arithmetic unit, a plurality of temporary storage means in the arithmetic unit for temporarily storing interim results of the arithmetic operation therein to relieve the influence of propagation delay time of the arithmetic unit.

Abstract: In a character displaying device having a character pattern memory which is made up of a circulating sequential access memory storing character patterns therein, a character pattern generating system comprises a high speed buffer memory which stores the character codes of one line or any other suitable amount of characters to be displayed and the corresponding character patterns, so that each time one character is delivered as an output from the character pattern memory, the presence of the character code of the particular character is examined for all the character codes of the buffer memory, and the character pattern of the particular character is written into the buffer memory when the character codes are coincident, the writing operations being sequentially executed in the order of the character outputs of the character pattern memory, thereby making it possible to finish all the character patterns in the buffer memory within a period in which the read-out of the character pattern memory circulates.

Abstract: An anti-skid control system for an automotive vehicle comprising apparatus for inhibiting the operation of anti-skid apparatus in a vehicle speed range lower than a predetermined value at which the full braking force can be imparted to the wheels without giving rise to any danger, so that the anti-skid control system can operate with improved reliability.