Patents by Inventor Noritaka Saitoh

Noritaka Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital PLL circuit having reduced lead-in time
    Patent number: 5012198
    Abstract: A digital PLL circuit to output a clock signal phase-synchronized with an input signal comprises a divider outputting the clock signal and a signal initiation pulse generator generating a signal to set the divider to a predetermined state depending on the input signal initiation. The maximum lead-in time is reduced to 1/n in comparison with prior art, and therefore the circuit is very suitable for use in the receiving part of a device which receives a burst data signal.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: April 30, 1991
    Assignee: Mitsubishi Rayon Company, Ltd.
    Inventors: Hiroshi Okada, Noritaka Saitoh, Hidetomo Akabane, Shintaro Tashiro