Abstract: Provided is a solid-state imaging device that suppresses propagation of a crack. There is provided a solid-state imaging device including: a first substrate on which a pixel unit configured to perform photoelectric conversion is formed; and a second substrate on which a logic circuit configured to process a pixel signal outputted from the pixel unit is formed, in which the first and second substrates are laminated by being connected by metal binding between wiring layers that are formed individually, an opening hole is formed on an outer periphery of the pixel unit to penetrate the first and second substrates to reach an upper part of a wire bonding pad formed in the second substrate, the second substrate includes an insulating layer below the wire bonding pad, and the insulating layer includes a first insulating film.

Abstract: According to one embodiment, a solid state imaging device includes a semiconductor layer, a first layer, a second layer and third layer. The semiconductor layer performs photoelectric conversion. The first layer has a first refractive index. The second layer is provided between the first layer and the semiconductor layer, the second layer includes a metal oxide and has a second refractive index not greater than the first refractive index. The third layer is provided between the first layer and the second layer. The third layer has a third refractive index and includes an element bonding covalently with oxygen. The third refractive index is not greater than the first refractive index.

Abstract: Certain embodiments provide a semiconductor device including a first line, a second line, and a sacrificial line. The second line is connected to the first line, and has a narrower linewidth than the first line. The sacrificial line is a wiring having its one end connected to the first line, and its another end as an open end. Further, the sacrificial line at least partially has a portion with a narrower linewidth than the second line.

Abstract: A semiconductor device includes: an insulating layer formed on a substrate; a plurality of interlayer insulating films which are formed on the insulating layer and comprise an opening window; a multilayer wiring which is formed with a plurality of wiring layers and a plurality of vias formed in the plurality of interlayer insulating films; a metal pad connected with the multilayer wiring, an upper surface part of the metal pad being a bottom part of the opening window, the metal pad formed closer to the substrate than a wiring layer of a lowermost layer of the plurality of wiring layers and is; and a pad ring provided on the metal pad, the pad ring penetrating the plurality of interlayer insulating films and the pad ring surrounding the opening window.

Abstract: According to one embodiment, a manufacturing method for a semiconductor device includes: forming a test pattern with a metal film embedded therein through a plating process; detecting a characteristic of the test pattern; and adjusting a condition for the plating process based on the detected characteristic of the test pattern. The test pattern is formed over three or more wiring layers and includes a stacked via in an intermediate layer.

Abstract: Certain embodiments provide a semiconductor device including a first line, a second line, and a sacrificial line. The second line is connected to the first line, and has a narrower linewidth than the first line. The sacrificial line is a wiring having its one end connected to the first line, and its another end as an open end. Further, the sacrificial line at least partially has a portion with a narrower linewidth than the second line.

Abstract: A semiconductor device includes: an insulating layer formed on a substrate; a plurality of interlayer insulating films which are formed on the insulating layer and comprise an opening window; a multilayer wiring which is formed with a plurality of wiring layers and a plurality of vias formed in the plurality of interlayer insulating films; a metal pad connected with the multilayer wiring, an upper surface part of the metal pad being a bottom part of the opening window, the metal pad formed closer to the substrate than a wiring layer of a lowermost layer of the plurality of wiring layers and is; and a pad ring provided on the metal pad, the pad ring penetrating the plurality of interlayer insulating films and the pad ring surrounding the opening window.

Abstract: An exposure system includes a exposure tool for projecting an image of a mask pattern onto a first resist with test values of a dose to form test resist patterns, a microscope for defining coordinates of mask positions along the mask pattern in a scan direction, measuring actual values of a mask line width of the mask pattern at the coordinates, and measuring actual values of a resist line width of each of the test resist patterns at projected positions, a collection module for collecting a relationship among the mask line width, the resist line width, and the dose at the coordinates, and a tool controller for controlling the exposure tool to project the image of the mask pattern onto a second resist with changing the dose depending on the coordinates to make the resist line width constant, based on the relationship.

Abstract: A method of manufacturing a semiconductor device has forming a first insulating film on a low dielectric constant film; etching the first insulating film and the low dielectric constant film to form a trench in a region in which the wiring layer is to be formed; forming a first barrier metal film in the trench and on the first insulating film; forming a film of a conductive material on the first barrier metal film, thereby burying the conductive material in the trench to form a conductor layer; polishing and planarizing the conductor layer, the first barrier metal film and the first insulating film by CMP using a slurry, wherein the first insulating film is not completely removed; and etching the remained first insulating film after the planarization by the CMP manner.

Abstract: An exposure system includes a exposure tool for projecting an image of a mask pattern onto a first resist with test values of a dose to form test resist patterns, a microscope for defining coordinates of mask positions along the mask pattern in a scan direction, measuring actual values of a mask line width of the mask pattern at the coordinates, and measuring actual values of a resist line width of each of the test resist patterns at projected positions, a collection module for collecting a relationship among the mask line width, the resist line width, and the dose at the coordinates, and a tool controller for controlling the exposure tool to project the image of the mask pattern onto a second resist with changing the dose depending on the coordinates to make the resist line width constant, based on the relationship.