Patents by Inventor Noritsugu Nakamura
Noritsugu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160042099Abstract: A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.Type: ApplicationFiled: October 26, 2015Publication date: February 11, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takao TOI, Taro FUJII, Noritsugu NAKAMURA
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Patent number: 9201996Abstract: A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.Type: GrantFiled: June 20, 2013Date of Patent: December 1, 2015Assignee: Renesas Electronics CorporationInventors: Takao Toi, Taro Fujii, Noritsugu Nakamura
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Publication number: 20130346929Abstract: A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.Type: ApplicationFiled: June 20, 2013Publication date: December 26, 2013Inventors: Takao TOI, Taro FUJII, Noritsugu NAKAMURA
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Patent number: 8516414Abstract: A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.Type: GrantFiled: March 24, 2009Date of Patent: August 20, 2013Assignee: NEC CorporationInventors: Yoshinosuke Kato, Takao Toi, Noritsugu Nakamura, Toru Awashima, Hirokazu Kami
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Patent number: 8176451Abstract: A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N?1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.Type: GrantFiled: September 29, 2009Date of Patent: May 8, 2012Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Taro Fujii, Toshiro Kitaoka, Koichiro Furuta, Masato Motomura
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Patent number: 8151089Abstract: A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.Type: GrantFiled: October 29, 2003Date of Patent: April 3, 2012Assignee: Renesas Electronics CorporationInventors: Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima, Takao Toi, Noritsugu Nakamura
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Patent number: 7696471Abstract: Disclosed is an impact detection system including: an optical fiber including a plurality of sensor sections to reflect light, a wavelength band of the reflected light vibrates depending on an elastic wave propagating through a subject to be inspected; a light source to input light into the optical fiber; optical filters each connected to an output terminal of the optical fiber; and an arithmetic processing unit to detect the impact from output values of sensor sections, wherein the wavelength bands of the sensor sections in the optical fiber are distributed such that the vibration bands caused by the impact to be detected do not overlap with each other, and a pass band of the optical filter corresponding to one of the sensor sections is distributed in the vibration band caused by the detection object, and is distributed in both sides of a center of the wavelength band of the one sensor section.Type: GrantFiled: November 30, 2007Date of Patent: April 13, 2010Assignees: Fuji Jukogyo Kabushiki Kaisha, The University of TokyoInventors: Toshimichi Ogisu, Noritsugu Nakamura, Nobuo Takeda
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Publication number: 20100083209Abstract: A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N?1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.Type: ApplicationFiled: September 29, 2009Publication date: April 1, 2010Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Takao TOI, Noritsugu NAKAMURA, Yoshinosuke KATO, Toru AWASHIMA, Taro FUJII, Toshiro KITAOKA, Koichiro FURUTA, Masato MOTOMURA
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Patent number: 7633052Abstract: Disclosed an impact detection system including: three or more optical fiber sensors disposed respectively in different positions, the sensors not being in alignment with one another, in which the sensors each includes a core portion to have a grating portion formed therein, the grating portion has a plurality of gratings; light source; two or more optical filters having different pass bands to one another to an output light of one of the optical fiber sensors; and an arithmetic processing apparatus to perform arithmetic processing of output values of the three or more optical fiber sensors through the optical filters so as to specify a position on the subject where an impact is loaded, the output values being obtained when the impact is loaded on the subject.Type: GrantFiled: November 30, 2007Date of Patent: December 15, 2009Assignees: Fuji Jukogyo Kabushiki Kaisha, The University of TokyoInventors: Noritsugu Nakamura, Toshimichi Ogisu, Nobuo Takeda
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Publication number: 20090249262Abstract: A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.Type: ApplicationFiled: March 24, 2009Publication date: October 1, 2009Inventors: Yoshinosuke Kato, Takao Toi, Noritsugu Nakamura, Toru Awashima, Hirokazu Kami
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Patent number: 7523292Abstract: A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.Type: GrantFiled: October 10, 2003Date of Patent: April 21, 2009Assignee: NEC Electronics CorporationInventors: Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima, Takao Toi, Noritsugu Nakamura
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Publication number: 20080129982Abstract: Disclosed an impact detection system including: three or more optical fiber sensors disposed respectively in different positions, the sensors not being in alignment with one another, in which the sensors each includes a core portion to have a grating portion formed therein, the grating portion has a plurality of gratings; light source; two or more optical filters having different pass bands to one another to an output light of one of the optical fiber sensors; and an arithmetic processing apparatus to perform arithmetic processing of output values of the three or more optical fiber sensors through the optical filters so as to specify a position on the subject where an impact is loaded, the output values being obtained when the impact is loaded on the subject.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Applicants: FUJI JUKOGYO KABUSHIKI KAISHA, THE UNIVERSITY OF TOKYOInventors: Noritsugu Nakamura, Toshimichi Ogisu, Nobuo Takeda
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Publication number: 20080128600Abstract: Disclosed is an impact detection system including: an optical fiber including a plurality of sensor sections to reflect light, a wavelength band of the reflected light vibrates depending on an elastic wave propagating through a subject to be inspected; a light source to input light into the optical fiber; optical filters each connected to an output terminal of the optical fiber; and an arithmetic processing unit to detect the impact from output values of sensor sections, wherein the wavelength bands of the sensor sections in the optical fiber are distributed such that the vibration bands caused by the impact to be detected do not overlap with each other, and a pass band of the optical filter corresponding to one of the sensor sections is distributed in the vibration band caused by the detection object, and is distributed in both sides of a center of the wavelength band of the one sensor section.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Applicants: Fuji Jukogyo Kabushiki Kaisha, The University of TokyoInventors: Toshimichi Ogisu, Noritsugu Nakamura, Nobuo Takeda
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Publication number: 20080040700Abstract: The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for processing at a logic synthesizing stage, placement and routing stage, debugging stage, writing stage of circuit information to a reconfigurable device, or the like, so as to use storage elements that are to be allocated to the variables described in the behavioral level description in common and to achieve optimization such as minimizing data paths and the like. Also in a debugger and in a writing device for writing circuit information, the aforementioned liveness information is used to execute a task of not displaying invalid variables, a task of reducing the amount of information to be saved to an external memory, etc.Type: ApplicationFiled: March 29, 2007Publication date: February 14, 2008Applicant: NEC CORPORATIONInventors: Yoshinosuke Katoh, Toru Awashima, Noritsugu Nakamura, Hirokazu Kami, Takao Toi
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Patent number: 7120903Abstract: An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.Type: GrantFiled: September 24, 2002Date of Patent: October 10, 2006Assignee: NEC CorporationInventors: Takao Toi, Toru Awashima, Yoshiyuki Miyazawa, Noritsugu Nakamura, Taro Fujii, Koichiro Furuta, Masato Motomura
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Publication number: 20040153625Abstract: In an array-type processor in which a multiplicity of processor elements, which each execute data processing in accordance with instruction codes in which data are individually set, are arranged in rows and columns, and in which state control units cause successive transitions of the operating states of this multiplicity of processor elements for each operating cycle by means of contexts that are make up by instruction codes, a plurality of element areas are respectively connected to an equal number of state control units, and state control units that correspond to a prescribed number of operating states that are set to one context temporarily halt the operation of element areas to which the state control unit is connected during operating cycle in which operating states do not occur.Type: ApplicationFiled: January 22, 2004Publication date: August 5, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima, Takao Toi, Noritsugu Nakamura
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Publication number: 20040107332Abstract: A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.Type: ApplicationFiled: October 29, 2003Publication date: June 3, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima, Takao Toi, Noritsugu Nakamura
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Publication number: 20040103264Abstract: A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.Type: ApplicationFiled: October 10, 2003Publication date: May 27, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima, Takao Toi, Noritsugu Nakamura
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Publication number: 20040078093Abstract: A multiplicity of processor elements, which individually execute data processing in accordance with instruction codes that are individually set and for which the connection relation between processor elements is switch-controlled, are arranged in a matrix; and the instruction codes of the multiplicity of processor elements are successively switched by a state control unit. The state control unit is composed of a plurality of units that intercommunicate to realize linked operation, the multiplicity of processor elements is divided into a plurality of element groups, and the plurality of state control units and the plurality of element groups are individually connected, whereby a plurality of small-scale state transitions can be individually controlled by the state control units, or a single large-scale state transition can be controlled through the cooperation of the plurality of state control units.Type: ApplicationFiled: October 10, 2003Publication date: April 22, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Taro Fujii, Koichiro Furuta, Masato Motomura, Kenichiro Anjo, Yoshikazu Yabe, Toru Awashima, Takao Toi, Noritsugu Nakamura
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Publication number: 20030126404Abstract: At least one of a plurality of data processors of a data processing system is an array-type processor, and the data processing of this array-type processor and the other data processors is effectively linked. The array-type processor and other data processors, which process the process data in accordance with event data and issue event data in accordance with this data processing, communicate to each other at least a portion of the process data and at least a portion of the event data and thus link the data processing.Type: ApplicationFiled: December 24, 2002Publication date: July 3, 2003Applicant: NEC CORPORATIONInventors: Kenichiro Anjo, Taro Fujii, Koichiro Furuta, Yoshikazu Yabe, Masato Motomura, Takao Toi, Toru Awashima, Noritsugu Nakamura