Patents by Inventor Noritsugu Ozaki
Noritsugu Ozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10210720Abstract: Electronic equipment includes: a substrate configured to include a first component, a second component, and an interconnection part that couples the first component with the second component by electric interconnections; and an exterior part configured to cover the first component, the second component, and the interconnection parts, and include a first exterior section that covers at least a portion of the first component, and a second exterior section that covers at least a portion of the interconnection parts, a thickness of the first exterior section being different from a thickness of the second exterior section to form a level difference in a boundary part between the first exterior section and the second exterior section.Type: GrantFiled: May 2, 2017Date of Patent: February 19, 2019Assignee: FUJITSU LIMITEDInventors: Takayoshi Matsumura, Shunji Baba, Takashi Kanda, Noritsugu Ozaki, Hidehiko Kira
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Patent number: 9974167Abstract: A wiring board includes: a base member having stretchability; and a wiring including a plurality of conductive thread-like members that are sewn in the base member in a meandering manner and do not have stretchability.Type: GrantFiled: November 2, 2017Date of Patent: May 15, 2018Assignee: FUJITSU LIMITEDInventors: Shunji Baba, Noritsugu Ozaki
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Publication number: 20180035536Abstract: A wiring board includes a base having extensibility and a wiring formed on the base. The wiring includes a wiring portion and a conductor portion. The wiring portion is formed on the base and extends in a first direction crossing (for example, perpendicular to) a longitudinal direction of the base. The conductor portion is formed on the wiring portion and extends in the first direction. Even when the wiring board is extended along a main extension axis in parallel with the longitudinal direction of the base, change of the resistance of the wiring is prevented. Thus, the wiring board represents stable characteristics.Type: ApplicationFiled: June 14, 2017Publication date: February 1, 2018Applicant: FUJITSU LIMITEDInventors: Takayoshi Matsumura, Shunji Baba, TAKASHI KANDA, NORITSUGU OZAKI, Hidehiko Kira
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Publication number: 20170345264Abstract: Electronic equipment includes: a substrate configured to include a first component, a second component, and an interconnection part that couples the first component with the second component by electric interconnections; and an exterior part configured to cover the first component, the second component, and the interconnection parts, and include a first exterior section that covers at least a portion of the first component, and a second exterior section that covers at least a portion of the interconnection parts, a thickness of the first exterior section being different from a thickness of the second exterior section to form a level difference in a boundary part between the first exterior section and the second exterior section.Type: ApplicationFiled: May 2, 2017Publication date: November 30, 2017Applicant: FUJITSU LIMITEDInventors: Takayoshi Matsumura, Shunji Baba, TAKASHI KANDA, NORITSUGU OZAKI, Hidehiko Kira
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Patent number: 9740976Abstract: An RFID tag includes a core formed by a first elastic material and having a first surface, a second surface on an opposite side of the first surface, and a pair of end parts provided on mutually opposite sides and connecting to the first surface and the second surface. The RFID tag further includes a metal layer provided on the first surface, a semiconductor chip provided on the second surface, and a dipole antenna provided on the second surface and electrically connected to the semiconductor chip. One of the metal layer and the dipole antenna is folded at folded parts at the pair of end parts, and the metal layer and the dipole antenna overlap at the folded parts.Type: GrantFiled: February 2, 2016Date of Patent: August 22, 2017Assignee: FUJITSU LIMITEDInventors: Noritsugu Ozaki, Shunji Baba, Takayoshi Matsumura
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Patent number: 9443187Abstract: An RFID tag includes an antenna, a first IC chip connected to the antenna, and a first fuse inserted between the antenna and the first IC chip, or inserted in series with the antenna. In the RFID tag, the first fuse becomes electrically conductive at a first temperature or above, and remains in an electrical conductive state after having become electrically conductive.Type: GrantFiled: March 28, 2014Date of Patent: September 13, 2016Assignee: FUJITSU LIMITEDInventor: Noritsugu Ozaki
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Publication number: 20160155041Abstract: An RFID tag includes a core formed by a first elastic material and having a first surface, a second surface on an opposite side of the first surface, and a pair of end parts provided on mutually opposite sides and connecting to the first surface and the second surface. The RFID tag further includes a metal layer provided on the first surface, a semiconductor chip provided on the second surface, and a dipole antenna provided on the second surface and electrically connected to the semiconductor chip. One of the metal layer and the dipole antenna is folded at folded parts at the pair of end parts, and the metal layer and the dipole antenna overlap at the folded parts.Type: ApplicationFiled: February 2, 2016Publication date: June 2, 2016Applicant: FUJITSU LIMITEDInventors: Noritsugu OZAKI, Shunji BABA, Takayoshi MATSUMURA
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Patent number: 9208425Abstract: An RFID tag including an inlay having a sheet-like shape and including an antenna and an IC chip electrically connected to the antenna, an outer covering member that covers the inlay, the outer covering member having a planar shape and including a main surface and a rear surface, and a frame part arranged on at least one of the main surface and the rear surface. The frame part is erected in a thickness direction of the outer covering member. The frame part surrounds the IC chip in a plan view.Type: GrantFiled: August 15, 2014Date of Patent: December 8, 2015Assignee: FUJITSU LIMITEDInventors: Takayoshi Matsumura, Kenzo Nishide, Shigeru Gotou, Noritsugu Ozaki, Shunji Baba
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Publication number: 20150060554Abstract: An RFID tag including an inlay having a sheet-like shape and including an antenna and an IC chip electrically connected to the antenna, an outer covering member that covers the inlay, the outer covering member having a planar shape and including a main surface and a rear surface, and a frame part arranged on at least one of the main surface and the rear surface. The frame part is erected in a thickness direction of the outer covering member. The frame part surrounds the IC chip in a plan view.Type: ApplicationFiled: August 15, 2014Publication date: March 5, 2015Inventors: Takayoshi Matsumura, Kenzo NISHIDE, Shigeru Gotou, NORITSUGU OZAKI, Shunji Baba
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Publication number: 20140209692Abstract: An RFID tag includes an antenna, a first IC chip connected to the antenna, and a first fuse inserted between the antenna and the first IC chip, or inserted in series with the antenna. In the RFID tag, the first fuse becomes electrically conductive at a first temperature or above, and remains in an electrical conductive state after having become electrically conductive.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Applicant: FUJITSU LIMITEDInventor: Noritsugu OZAKI
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Patent number: 8424771Abstract: An RFID tag includes a semiconductor package, a substrate and an antenna pattern. The semiconductor package includes a semiconductor chip encapsulated therein and a plurality of connection terminals thereon. The plurality of connection terminals includes signal terminals and dummy terminals. The semiconductor package is mounted on the substrate. The antenna pattern is formed on the substrate and is electrically connected to the signal terminals. The antenna pattern is extended so as to overlap with at least a part of a bottom region of the semiconductor package.Type: GrantFiled: June 28, 2010Date of Patent: April 23, 2013Assignees: Fujitsu Limited, Fujitsu Frontech LimitedInventors: Shunji Baba, Noritsugu Ozaki, Manabu Kai, Satoru Nogami, Yoshiyasu Sugimura
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Publication number: 20110068904Abstract: An RFID tag includes: a tabular dielectric member 11; an antenna pattern 12 that extends over a top surface and an undersurface of the dielectric member and forms a loop antenna L1 having both ends existing on one surface of the top surface and the undersurface; a circuit chip 13 that is electrically connected to the antenna pattern; a first electrode 14 that is connected directly or via a conductor to one end 12a of the both ends of the loop antenna and spreads on the one surface of the top surface and the undersurface; and a second electrode 15 that is connected via a conductor to the other end 12b of the both ends of the loop antenna and spreads on the other surface of the top surface and the undersurface, along the first electrode 14.Type: ApplicationFiled: December 2, 2010Publication date: March 24, 2011Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Shunji Baba, Noritsugu Ozaki, Toru Maniwa, Manabu Kai, Yoshiyasu Sugimura, Satoru Nogami
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Publication number: 20110001608Abstract: An RFID tag includes a semiconductor package, a substrate and an antenna pattern. The semiconductor package includes a semiconductor chip encapsulated therein and a plurality of connection terminals thereon. The plurality of connection terminals includes signal terminals and dummy terminals. The semiconductor package is mounted on the substrate. The antenna pattern is formed on the substrate and is electrically connected to the signal terminals. The antenna pattern is extended so as to overlap with at least a part of a bottom region of the semiconductor package.Type: ApplicationFiled: June 28, 2010Publication date: January 6, 2011Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Shunji BABA, Noritsugu OZAKI, Manabu KAI, Satoru NOGAMI, Yoshiyasu SUGIMURA
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Patent number: 6109507Abstract: A method of forming solder bumps on pads provided on a board, wherein a plurality of solder bump layer forming cycles are repeatedly implemented. Each of the solder bump layer forming cycles includes the steps of printing solder paste on the board using a mask having mask openings and heating the solder paste so as to fuse the solder paste for forming solder bumps.Type: GrantFiled: May 15, 1998Date of Patent: August 29, 2000Assignee: Fujitsu LimitedInventors: Harumi Yagi, Noritsugu Ozaki, Tsuyoshi Yamamoto, Toshiyuki Nakada, Takeshi Komiyama, Yoshihito Okuwaki