Abstract: A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

Abstract: A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

Abstract: A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

Abstract: A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

Abstract: A pneumatic tire is provided including a multiplicity of land portions 3A, 3B, 3C, 3D, and 3E formed by main grooves 2 extending linearly in the tire width direction partitioning the tread surface 1, and having a designated mounting direction on a vehicle. Among the multiplicity of land portions 3A, 3B, 3C, 3D, and 3E, lug grooves are not provided in a ground contact region R of the land portions 3A and 3E positioned on both shoulder sides. Lug grooves 4 inclining in the tire circumferential direction that have terminating parts in the land portions and opening to the main groove 2 on the vehicle inner side are formed at specified intervals in the tire circumferential direction in the land portions 3B and 3D inwardly adjacent to the land portions on both shoulder sides.

Abstract: A pneumatic tire is provided including a multiplicity of land portions 3A, 3B, 3C, 3D, and 3E formed by main grooves 2 extending linearly in the tire width direction partitioning the tread surface 1, and having a designated mounting direction on a vehicle. Among the multiplicity of land portions 3A, 3B, 3C, 3D, and 3E, lug grooves are not provided in a ground contact region R of the land portions 3A and 3E positioned on both shoulder sides. Lug grooves 4 inclining in the tire circumferential direction that have terminating parts in the land portions and opening to the main groove 2 on the vehicle inner side are formed at specified intervals in the tire circumferential direction in the land portions 3B and 3D inwardly adjacent to the land portions on both shoulder sides.

Abstract: In a semiconductor integrated circuit device including a semiconductor integrated circuit board having a mask ROM area and an internal bus and a programmable ROM which is mounted on the semiconductor integrated circuit board and which has a plurality of ROM connecting terminals, the ROM connecting terminals are electrically connected to a plurality of bus connecting terminals connected to the internal bus, respectively. The bus connecting terminals may be disposed around periphery of the semiconductor integrated circuit board, may be formed on the mask ROM area, and may be disposed on the internal bus. In this event, the ROM connecting terminals and the bus connecting terminals are electrically connected to each other using wire bonding technique.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: The present invention relates to a polyamide resin composition comprising: 100 parts by weight of a polyamide resin mixture comprising (A) 20 to 90% by weight of a polyamide 6 resin, a polyamide 66 resin or mixture thereof and (B) 10 to 80% by weight of an aromatic polyamide resin; and (C) 0 to 300 parts by weight of an inorganic filler, said aromatic polyamide resin being having diamine units comprising 10 to 50 mol % of paraxylylenediamine units and 50 to 90 mol % of methaxylylenediamine units, and aliphatic dicarboxylic acid units.

Abstract: To a first signal line to which a signal with a comparable small amplitude against the power supply voltage is transmitted at a first timing, a second signal line to which a voltage maintained at a constant is transmitted at the first timing is laid out on the same wiring layer as that of the first signal line adjacently to each other. Thereby, the invention reduces the coupling noises without impairing a high density of the signal wirings, and provides a semiconductor integrated circuit device with a memory circuit that realizes a high integration, low power consumption, and high speed.

Abstract: A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair of writing signal lines so that the signal to be written is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.