Abstract: A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 ?m. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.

Abstract: A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode.

Abstract: A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time.

Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

Abstract: A semiconductor device includes a peripheral voltage withstanding structure, which includes an n? SiC layer, an n SiC layer and a p SiC layer are provided successively on an n+ SiC layer. A trench is formed in the peripheral voltage withstanding structure portion so that the trench passes through the p SiC layer 15 and the n SiC layer 14 and reaches the n? SiC layer. This trench is wider than a trench having a trench gate structure in the active region portion. A p+ SiC region is provided along a bottom of the trench so as to be located under the trench. A sidewall and the bottom of the trench are covered with an oxide film and an insulating film having a total thickness not smaller than 1.1 ?m. The oxide film and insulating film absorb a large part of a voltage applied between a source and a drain.

Abstract: A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode.

Abstract: A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

Abstract: A gallium nitride semiconductor device is disclosed that can be made by an easy manufacturing method. The device includes a silicon substrate, buffer layers formed on the top surface of the silicon substrate, and gallium nitride grown layers formed thereon. The silicon substrate has trenches 12 formed from the bottom surface, each trench having a depth reaching the gallium nitride grown layer through the silicon substrate and the buffer layers. The inside surface of each of the trenches and the bottom surface of the silicon substrate is covered with a drain electrode as a metal film. The vertical gallium nitride semiconductor device with this structure allows an electric current to flow in the direction of the thickness of the silicon substrate regardless of the resistance values of the gallium nitride grown layers and the buffer layers.

Abstract: A semiconductor device and a method of forming the semiconductor device include a substrate and an n drift layer on the substrate with an insulator film placed between them. A trench is provided in a section between a p base region and an n buffer layer on the surface layer of the n drift layer. Moreover, the distance between the bottom of the trench and the insulator film on the substrate is 1 ?m or more and 75% or less than the thickness of the n drift layer. This reduces the ON-state Voltage Drop and enhances the device breakdown voltage and the latch up current in a lateral IGBT or a lateral MOSFET.

Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

Abstract: A semiconductor device is provided which includes a first p base region and a second p base region formed in one of opposite surface of a high-resistance n base region, a p collector region formed on the other surface of the n base region, an n emitter region formed in a surface layer of the first p base region, and a groove formed in the n base region between the first and second p base regions, to provide a trench gate electrode portion. The first and second p base regions are formed alternately in the Z-axis direction with certain spacing therebetween. The second p base region is held in a floating state in terms of the potential, thus assuring a reduced ON-resistance, and a large quantity of carriers present in the vicinity of the surface of the second p base region are quickly drawn away through a p channel upon turn-off, so that the turn-off time is reduced.

Abstract: A semiconductor device is provided which includes a first p base region and a second p base region formed in one of opposite surface of a high-resistance n base region, a p collector region formed on the other surface of the n base region, an n emitter region formed in a surface layer of the first p base region, and a groove formed in the n base region between the first and second p base regions, to provide a trench gate electrode portion. The first and second p base regions are formed alternately in the Z-axis direction with certain spacing therebetween. The second p base region is held in a floating state in terms of the potential, thus assuring a reduced ON-resistance, and a large quantity of carriers present in the vicinity of the surface of the second p base region are quickly drawn away through a p channel upon turn-off, so that the turn-off time is reduced.

Abstract: To provide a semiconductor device that has a positive ON-voltage temperature coefficient and a high switching speed at the current densities provided during actual operation. A (p) anode layer 1 is formed on one surface of an (n) base layer 3 having high resistance, and an (n) cathode layer 2 is formed on the other surface. The surface of the (p) anode layer 1 is coated with an insulating film having contact slots formed therein, and the anode electrode 5 is formed on the (p) anode layer 1 and is fixed to the (p) anode layer 1 at the locations of the contact slots 7. A cathode electrode 6 is formed on the (n) cathode layer 2. In addition, the planar pattern of the contact slots 7 is shaped like stripes. The area ratio S1/S2 is 5 or more and 30 or less, where area S1 constitutes the (p) anode layer 1 that is occupied by an insulating film 4 (the area of a non-secured portion), and area S2 represents the locations of the contact slots 7 (the area of the secured portion).

Abstract: A plurality of optimized diode chips are connected in series with each other to provide a high-voltage silicon diode rectifying device. Each chip has an improved withstand voltage and inverse surge resistance which improves the overall usefulness and efficiency of high-voltage silicon diodes. This invention also reduces costs by requiring fewer individual diode chips. The specific resistance of the (n)-type silicon substrate is in a critical range of between 20 to 50 &OHgr;cm. The diffusion depth of the p+ anode layer is in a critical range of between 30 to 200 &mgr;m. The thickness of the n− base layer is 0.54×(&rgr;·Vsr)½ or greater. In another embodiment, the specific resistance of the silicon substrate is in the range of 32 to 40 &OHgr;cm, and diffusion depth of the p+ anode layer is in the range of 70 to 200 &mgr;m. In yet another embodiment, a cathode layer is diffused on the semiconductor base material.

Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.

Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.

Abstract: A insulated gate bipolar transistor comprising a semiconductor substrate layer having an impurity concentration of not less than 4.0.times.10.sup.13 /cm.sup.3, and being substantially free of lifetime killers.

Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.

Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.