Abstract: In a radio communication system having a phase control loop for phase modulation and an amplitude control loop for amplitude modulation and being capable of time divisional transmission and reception under a predetermined time management, when transmission in a first mode is switched to transmission in a second mode or when transmission in the second mode is switched to transmission in the first mode, the output level of the power amplifier is lowered once to a predetermined level higher than the level when transmission related circuits are activated, and thereafter the output level of the power amplifier is again ramped after the settings have been changed but without starting of a transmission oscillator, establishing of the phase control loop and the amplitude control loop.

Abstract: The invention provides a communication semiconductor integrated circuit (RF IC) that, when a transmission oscillator is incorporated into a semiconductor chip, secures the oscillation operation over a wide frequency range, prevents a deterioration of a transmission spectrum, and thereby enhances the accuracy of an oscillation frequency. The integrated circuit corrects a dispersion of the KV characteristic of the transmission oscillator by calibrating a current Icp of the charge pump inside the phase control loop. More in concrete, the integrated circuit measures a KV value Kv of the transmission oscillator, and calibrates the current Icp of the charge pump so that Kv·Icp falls into a predetermined value.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit for the transmission PLL circuit is configured to be operable in a plurality of bands. The communication semiconductor integrated circuit also comprises a circuit for measuring the oscillating frequency of the oscillator circuit for the transmission PLL circuit, and a storage circuit for storing the result of measurement made by the measuring circuit. A band to be used by the oscillator circuit for the transmission PLL circuit is determined based on values for setting the oscillating frequencies of the oscillator circuit forming part of the reception PLL circuit and the intermediate frequency oscillator circuit, and the result of measurement stored in the storage circuit.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.

Abstract: In a polar loop based radio-communications apparatus having a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmission, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplification circuit, the phase control loop is first started while maintaining the amplitude control loop in an off state at the outset of transmission, and the amplitude control loop is started after stabilizing the phase control loop.

Abstract: The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained.

Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.

Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.