Abstract: A database stores interface transfer capacity information in which calculation formulas for calculation of a data transfer capacity are described, correspondingly to types of interface circuits. A transfer time evaluation unit acquires a calculation formula corresponding to a type of a specified interface circuit which has been specified from among a plurality of interface circuits as an interface circuit to connect a plurality of arithmetic operational devices among which execution of a plurality of arithmetic operation processes is divided, from the interface transfer capacity information, and calculates the data transfer capacity of the specified interface circuit by using the acquired calculation formula.

Abstract: A processing dividing unit (130) extracts, from a function model (210) including one or more loop processes, each of the one or more loop processes. A parameter extracting unit (140) determines the characteristics of each extracted loop process. A performance calculation basic formula selecting unit (150) selects, for each loop process, from a plurality of processing time calculation procedures for calculating a processing time, a processing time calculation procedure for calculating a processing time of each loop process, based on the characteristics of each loop process and the architecture of computational resources executing the function model (210). A performance estimating unit (160) calculates a processing time of each loop process by using a corresponding processing time calculation procedure selected by the performance calculation basic formula selecting unit (150).

Abstract: An analysis unit divides hierarchized program code into a plurality of program elements in accordance with a predetermined division condition, analyzes each of the plurality of program elements, and extracts an attribute of each program element and a hierarchy of the plurality of program elements. A functional module extraction unit performs machine learning on the basis of the attribute of each program element and the hierarchy of the plurality of program elements extracted by the analysis unit and groups the plurality of program elements into a plurality of groups.

Abstract: A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.

Abstract: A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.

Abstract: An apparatus and method that improve design efficiency when designing an LSI. A selector module generating section inputs IP connection information describing input/output flows of signals between IPs included in an LSI to be designed, analyzes the inputted IP connection information, and generates a selector module of a selector that matches the input/output flows of signals between IPs described in the IP connection information. A macro module generating section generates a macro module in which relationships between the selector and function blocks are indicated, using the selector module generated by the selector module generating section.

Abstract: A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires the number of stages of input FFs of FF reception. A latency re-adjusting part obtains an optimum delay based on the above-mentioned necessary delay and input delay. A former-stage module analyzing part detects, based on the above-mentioned synthetic log or HDL, a state having a minimum total number of FFs. An FF insertion optimizing synthesis part subjects an entire circuit to high level synthesis again based on the above-mentioned optimum delay and an FF inserting position obtained based on the state having the minimum number of FFs, to thereby obtain optimized HDL.

Abstract: An apparatus and method that improve design efficiency when designing an LSI. A selector module generating section inputs IP connection information describing input/output flows of signals between IPs included in an LSI to be designed, analyzes the inputted IP connection information, and generates a selector module of a selector that matches the input/output flows of signals between IPs described in the IP connection information. A macro module generating section generates a macro module in which relationships between the selector and function blocks are indicated, using the selector module generated by the selector module generating section.

Abstract: A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires the number of stages of input FFs of FF reception. A latency re-adjusting part obtains an optimum delay based on the above-mentioned necessary delay and input delay. A former-stage module analyzing part detects, based on the above-mentioned synthetic log or HDL, a state having a minimum total number of FFs. An FF insertion optimizing synthesis part subjects an entire circuit to high level synthesis again based on the above-mentioned optimum delay and an FF inserting position obtained based on the state having the minimum number of FFs, to thereby obtain optimized HDL.

Abstract: A table device includes a match cell number output unit 25 for outputting a match cell number showing a cell PE which outputs a matching signal, and an address decoder 26 for specifying a node from among nodes in a search tree which construct a conversion table, the node corresponding to the match cell number. The table device acquires a data conversion value assigned to the above-mentioned node from a configuration memory 21, and, when the data conversion value is data showing a coded result or the like, outputs the data conversion value to outside the table device, whereas when the data conversion value is a branch code of the search tree, updates the cell PE to which a comparison instruction signal is furnished.

Abstract: A table device includes a match cell number output unit 25 for outputting a match cell number showing a cell PE which outputs a matching signal, and an address decoder 26 for specifying a node from among nodes in a search tree which construct a conversion table, the node corresponding to the match cell number. The table device acquires a data conversion value assigned to the above-mentioned node from a configuration memory 21, and, when the data conversion value is data showing a coded result or the like, outputs the data conversion value to outside the table device, whereas when the data conversion value is a branch code of the search tree, updates the cell PE to which a comparison instruction signal is furnished.

Abstract: The multiplexer device comprises a multiplexing means for multiplexing a plurality types of media information and outputting a multiplexed bit stream, a priority deciding means for deciding priority corresponding to each of the media information, and a multiplexing controller for controlling multiplexing of each of the media information according to the multiplexing means based on the priority decided by the priority deciding means. In addition the priority in each information is multiplexed.