Abstract: A display device includes substrates, pixels, an inter-pixel light blocking portion, a spacer, a spacer non-arranged portion, and a spacer arranged portion. The pixels are arranged in each of a first direction and a second direction perpendicular to each other. The inter-pixel light blocking portion includes at least one first partition portion partitioning the pixels arranged in the first direction and at least one second partition portion partitioning the pixels arranged in the second direction. The spacer is disposed between the substrates. The spacer non-arranged portion in which the spacer is not arranged is included in the first partition portion. The spacer arranged portion in which the spacer is arranged is included in the first partition portion. The spacer arranged portion wider than the spacer non-arranged portion has a formation area straddling the second partition portion with respect to the second direction.

Abstract: A display device includes substrates, pixels, an inter-pixel light blocking portion, a spacer, a spacer non-arranged portion, and a spacer arranged portion. The pixels are arranged in each of a first direction and a second direction perpendicular to each other. The inter-pixel light blocking portion includes at least one first partition portion partitioning the pixels arranged in the first direction and at least one second partition portion partitioning the pixels arranged in the second direction. The spacer is disposed between the substrates. The spacer non-arranged portion in which the spacer is not arranged is included in the first partition portion. The spacer arranged portion in which the spacer is arranged is included in the first partition portion. The spacer arranged portion wider than the spacer non-arranged portion has a formation area straddling the second partition portion with respect to the second direction.

Abstract: In the case where input terminals of a display driver circuit are compatible with two or more types of interface specifications, an LSI chip, which is the display driver circuit, has some input terminals connected to parallel data lines and its output terminals connected to display lines, and these input terminals and output terminals are arranged along a long side located on the display portion side. In at least one example embodiment, the rest of the input terminals, which are intended for parallel interface, are arranged along a long side located on the FPC board side. With this configuration, the long sides of the LSI chip can be rendered shorter (than in the case where all input terminals are arranged in a row) without causing malfunction.

Abstract: Provided is a liquid crystal display device 10 that divides “3m” video signal lines into groups of three lines according to an order of arrangement, and drives the video signal lines in the group within one horizontal period in a time-division manner. A pixel array 17 is configured such that columns each including pixel circuits for left eye 21 arranged along a vertical direction of a display screen and columns each including pixel circuits for right eye 22 arranged along the vertical direction of the display screen are arranged along a horizontal direction of the display screen. When driving the video signal lines in a time-division manner, a writing order to pixel circuits 18 within one horizontal period and a polarity of a voltage to be applied to the pixel circuits 18 are changed every two scanning signal lines. This improves image quality of both an image for left eye and an image for right eye, thereby improving image quality in stereoscopic display.

Abstract: The present invention relates to a display device and, more particularly, to an active matrix-type display device employing a line inversion drive scheme as a drive scheme. In a liquid crystal display device employing the line inversion drive scheme as a drive scheme, a predetermined video signals are applied to video signal lines in a predetermined period after start of a vertical blanking period. When a vertical scanning period starts in an even-numbered frame, a source potential (VS) decreases by ½ of amplitude in an effective video period. After the decreased source potential (VS) is maintained only for one horizontal scanning period, source bus lines are set to a high-impedance state. When a vertical scanning period starts in an odd-numbered frame, the source potential (VS) rises by ½ of amplitude in the effective video period. After the risen source potential VS is maintained only in one horizontal scanning period, the source bus lines are set to a high-impedance state.

Abstract: An input position detection system (1) according to the present invention includes a laser pointer (50) that emits infrared light, and a liquid crystal display device (10) that detects a position of an input from the input pointer (50) by detecting the infrared light. The liquid crystal display device (10) includes optical sensor elements (30), a received light intensity calculation circuit (31), a coordinate extracting circuit (32), a combining and calculating circuit (33), an input signal calculation circuit (35), and the like. The combining and calculating circuit (33) calculates the intensities of received light at respective coordinate positions on the basis of the information obtained by the coordinate extracting circuit (32) and the received light intensity calculation circuit (31).

Abstract: In the case where input terminals of a display driver circuit are compatible with two or more types of interface specifications, an LSI chip, which is the display driver circuit, has some input terminals connected to parallel data lines and its output terminals connected to display lines, and these input terminals and output terminals are arranged along a long side located on the display portion side. In at least one example embodiment, the rest of the input terminals, which are intended for parallel interface, are arranged along a long side located on the FPC board side. With this configuration, the long sides of the LSI chip can be rendered shorter (than in the case where all input terminals are arranged in a row) without causing malfunction.

Abstract: Provided is a liquid crystal display device 10 that divides “3m” video signal lines into groups of three lines according to an order of arrangement, and drives the video signal lines in the group within one horizontal period in a time-division manner. A pixel array 17 is configured such that columns each including pixel circuits for left eye 21 arranged along a vertical direction of a display screen and columns each including pixel circuits for right eye 22 arranged along the vertical direction of the display screen are arranged along a horizontal direction of the display screen. When driving the video signal lines in a time-division manner, a writing order to pixel circuits 18 within one horizontal period and a polarity of a voltage to be applied to the pixel circuits 18 are changed every two scanning signal lines. This improves image quality of both an image for left eye and an image for right eye, thereby improving image quality in stereoscopic display.

Abstract: The present invention relates to a display device and, more particularly, to an active matrix-type display device employing a line inversion drive scheme as a drive scheme. In a liquid crystal display device employing the line inversion drive scheme as a drive scheme, a predetermined video signals are applied to video signal lines in a predetermined period after start of a vertical blanking period. When a vertical scanning period starts in an even-numbered frame, a source potential (VS) decreases by ½ of amplitude in an effective video period. After the decreased source potential (VS) is maintained only for one horizontal scanning period, source bus lines are set to a high-impedance state. When a vertical scanning period starts in an odd-numbered frame, the source potential (VS) rises by ½ of amplitude in the effective video period. After the risen source potential VS is maintained only in one horizontal scanning period, the source bus lines are set to a high-impedance state.