Patents by Inventor Noriyuki Sato
Noriyuki Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978762Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.Type: GrantFiled: March 14, 2022Date of Patent: May 7, 2024Assignee: KEPLER COMPUTING INC.Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
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Publication number: 20240122202Abstract: The invention provides a chocolate having strong aroma characteristics. The aroma characteristics may include at least one of a fruity aroma and a floral aroma, and isoamyl acetate may be contained as an aroma component. The invention also provides a novel method for producing a chocolate having strong aroma characteristics. The method includes a step of crushing at least a cacao raw material and a sugar raw material in a sealed crusher.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Applicant: MEIJI CO., LTD.Inventors: Takashi KATAGIRI, Masayuki SATO, Keisuke KIMURA, Noriyuki MANADA
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Patent number: 11961877Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.Type: GrantFiled: December 14, 2021Date of Patent: April 16, 2024Assignee: KEPLER COMPUTING INC.Inventors: Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Pratyush Pandey, Jason Y. Wu, Sasikanth Manipatruni
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Patent number: 11955153Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.Type: GrantFiled: March 15, 2022Date of Patent: April 9, 2024Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
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Patent number: 11955560Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.Type: GrantFiled: June 26, 2020Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
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Patent number: 11955512Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.Type: GrantFiled: December 15, 2021Date of Patent: April 9, 2024Assignee: Kepler Computing Inc.Inventors: Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Pratyush Pandey, Jason Y. Wu, Sasikanth Manipatruni
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Patent number: 11942133Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: September 2, 2021Date of Patent: March 26, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11935700Abstract: A laminated electronic component includes an element body formed by laminating an insulating layer and having a bottom surface used as a mounting surface, and a bottom surface electrode formed on the bottom surface of the element body and containing glass and a sintered metal. The bottom surface electrode includes a first electrode layer and a second electrode layer formed on the element body side from the first electrode layer, an edge portion of the second electrode layer is covered with an overcoat layer which is a part of the element body, the first electrode layer is laminated on the second electrode layer with the overcoat layer interposed therebetween, and a content of glass in the first electrode layer is larger than a content of glass in the second electrode layer.Type: GrantFiled: March 22, 2022Date of Patent: March 19, 2024Assignee: TDK CORPORATIONInventors: Noriyuki Saito, Osamu Hirose, Toru Yoshida, Yoshinori Sato, Akira Suda, Akira Nakamura
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Patent number: 11930136Abstract: A reading device includes: plural transport rolls that transport a document along a transport path, include a discharge roll disposed on a most downstream side of the transport path, and rotate and do not rotate in synchronization with one another; an opening and closing unit that exposes or covers an upstream portion of the transport path; plural detectors that are provided apart from one another along the transport path, detect a transported document, and include a discharge detector that is disposed on a most downstream side of the transport path and is disposed on an upstream side relative to the discharge roll in a document transport direction; a reader that reads an image formed on a transported document in a downstream portion of the transport path; and a controller that stops the plural transport rolls once upon occurrence of a document jam inside a device body by controlling the transport rolls and rotates the transport rolls for only a predetermined period in a case where the discharge detector is dType: GrantFiled: December 2, 2021Date of Patent: March 12, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Noriyuki Obara, Hidemasa Takahashi, Kazunobu Sato, Shigeru Tamura, Yuki Iguchi
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Patent number: 11908704Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.Type: GrantFiled: February 1, 2022Date of Patent: February 20, 2024Assignee: KEPLER COMPUTING INC.Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, Fnu Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
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Patent number: 11910618Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.Type: GrantFiled: March 11, 2022Date of Patent: February 20, 2024Assignee: KEPLER COMPUTING INC.Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
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Patent number: 11901728Abstract: A power source supply control device includes controllable switch units configured to switch provision or non-provision of power source electric power supply to respective loads from a main power source, load monitor units configured to monitor a state in each of one or more of the loads connected to downstream sides of switch units, and a switch control unit configured to control on/off of each of the switch units sequentially, based on monitor situations of the load monitor units, in which the switch control unit specifies an energization switching order to the loads according to a predetermined state.Type: GrantFiled: February 28, 2020Date of Patent: February 13, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Noriyuki Sato, Takayuki Furuya
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Patent number: 11903219Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.Type: GrantFiled: March 11, 2022Date of Patent: February 13, 2024Assignee: KEPLER COMPUTING INC.Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
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Patent number: 11894417Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.Type: GrantFiled: February 3, 2022Date of Patent: February 6, 2024Assignee: KEPLER COMPUTING INC.Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
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Patent number: 11869843Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11871583Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: September 17, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11869928Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 14, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11871584Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11862517Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11854593Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: September 17, 2021Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni