Patents by Inventor Noriyuki Shikina

Noriyuki Shikina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179436
    Abstract: A photoelectric conversion apparatus includes a first AD conversion circuit and a second AD conversion circuit. A first analog signal group output from a first pixel group in the first scanning is input to the first AD conversion circuit and the second AD conversion circuit. A second analog signal group output from the second pixel group in the second scanning is input to the first AD conversion circuit and the second AD conversion circuit. The first AD conversion circuit and the second AD conversion circuit each include a comparator to which the first analog signal group is not input in the first scanning and the second analog signal group is input in the second scanning. The first AD conversion circuit is arranged on one end side of output lines, and the second AD conversion circuit is arranged on the other end side of the output lines.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 30, 2024
    Inventors: HIROAKI TANIGUCHI, YOSHIKO SHIGIYA, NORIYUKI SHIKINA
  • Publication number: 20240155268
    Abstract: A photoelectric conversion device including pixels, a scanning circuit and a controller is provided. The scanning circuit performs a driving operation including a first scan of causing the pixels to start an accumulation operation and a second scan of reading out signals from the pixels. The second scan includes first and second driving operations that are different in a length of a readout period. The controller is configured to supply, to the scanning circuit, a first synchronization signal for controlling the first scan and a second synchronization signal for controlling the second scan. A relationship between a cycle of the first synchronization signal and the second synchronization signal in the first driving operation and a cycle of the first synchronization signal and the second synchronization signal in the second driving operation is a non-integer multiple or a non-integral submultiple.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 9, 2024
    Inventors: YOSHIKO SHIGIYA, NORIYUKI SHIKINA, ATSUSHI SHIMADA
  • Patent number: 11972718
    Abstract: A display device displays an image in which each frame is formed by at least two subframes. The display device includes a drive unit configured to drive a plurality of pixels in a pixel array so as to drive pixels in at least two rows based on pixel data of each row of each supplied subframe data. The drive unit drives the plurality of pixels so as to cause pixels in a row not matching a row in the supplied current subframe data to emit light with a first condition, and cause pixels in a row matching the row in the current subframe data to emit light with a second condition. The second condition is a condition in which a light emission amount is larger than in the first condition when causing the pixels to emit light in accordance with identical pixel values.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: April 30, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunori Matsuyama, Noriyuki Shikina
  • Publication number: 20240111146
    Abstract: A photoelectric conversion device is provided. The device includes a pixel array in which pixels are arranged, a drive controller configured to drive the pixel array, a horizontal transfer unit configured to sequentially output analog signals respectively output from columns of the pixel array, an AD converter configured to convert an analog signal output from the horizontal transfer unit into a digital signal, a first clock generator configured to generate a clock signal used to control an operation of the drive controller, and a second clock generator configured to generate a clock signal used to control the horizontal transfer unit and the AD converter. A clock tree in which a clock signal is distributed from the first clock generator and a clock tree in which a clock signal is distributed from the second clock generator form clock trees different from each other.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 4, 2024
    Inventors: KAZUNORI MATSUYAMA, NORIYUKI SHIKINA
  • Patent number: 11843887
    Abstract: An apparatus includes a plurality of pixels, a comparator configured to compare an output signal of each of the plurality of pixels with a reference signal, and a counter of K bits (K is a natural number) configured to operate in parallel with operation of the comparator. The apparatus converts the output signal of each of the plurality of pixels into a digital signal using an output of the comparator and an output of the counter. The apparatus includes an addition unit configured to add a plurality of the digital signals. The addition unit includes a serial binary adder of M bits (M is a natural number less than K).
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: December 12, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Noriyuki Shikina
  • Publication number: 20230395629
    Abstract: An imaging device includes pixels each of which includes a microlens and a plurality of photoelectric conversion units. The pixels include a first pixel and a second pixel adjacent to the first pixel, a first photoelectric conversion unit included in the first pixel and a second photoelectric conversion unit included in the second pixel are configured to share a first floating diffusion unit, sensitivity of the second photoelectric conversion unit is lower than sensitivity of the first photoelectric conversion unit in a wavelength range in which the first photoelectric conversion unit has a peak of the sensitivity, and a charge of a photoelectric conversion unit other than the first photoelectric conversion unit and the second photoelectric conversion unit is read from a floating diffusion unit different from the first floating diffusion unit in each of the first pixel and the second pixel.
    Type: Application
    Filed: May 22, 2023
    Publication date: December 7, 2023
    Inventors: KAZUNORI MATSUYAMA, NORIYUKI SHIKINA
  • Publication number: 20230298506
    Abstract: A display device displays an image in which each frame is formed by at least two subframes. The display device includes a drive unit configured to drive a plurality of pixels in a pixel array so as to drive pixels in at least two rows based on pixel data of each row of each supplied subframe data. The drive unit drives the plurality of pixels so as to cause pixels in a row not matching a row in the supplied current subframe data to emit light with a first condition, and cause pixels in a row matching the row in the current subframe data to emit light with a second condition. The second condition is a condition in which a light emission amount is larger than in the first condition when causing the pixels to emit light in accordance with identical pixel values.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 21, 2023
    Inventors: KAZUNORI MATSUYAMA, NORIYUKI SHIKINA
  • Patent number: 11758296
    Abstract: Provided is a photoelectric conversion device including: a plurality of pixel circuits each including a photoelectric conversion unit configured to generate charges by photoelectric conversion and a transistor configured to transfer the charges from the photoelectric conversion unit; and a plurality of exposure control circuits each including a capacitor configured to hold a signal corresponding to an exposure period in the photoelectric conversion unit and a comparator circuit configured to compare a potential of a first terminal of two terminals of the capacitor with a threshold potential. Each of the plurality of exposure control circuits controls an exposure period of the photoelectric conversion unit by outputting a signal based on a comparison result caused by the comparator circuit to a control terminal of the transistor and driving the transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 12, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Noriyuki Shikina, Shinya Igarashi
  • Patent number: 11716550
    Abstract: An imaging arrangement comprising: a plurality of pixels arranged in a matrix; and a signal processing arrangement. A first and a second line of the matrix each comprise a light-receiving pixel and a reference pixel, the light-receiving pixels each receive incident light and output a light signal based on the incident light, and each reference pixel outputs a pixel signal for forming an address signal. The processing arrangement provides a first address signal and a second address signal, wherein: the first address signal indicates the position of the first line and comprises a signal value based on the pixel signal from the first line; and the second address signal indicates the position of the second line and comprises a signal value based on the pixel signal from the second line; and the signal value of the first address signal is different to the signal value of the second address signal.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 1, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Shikina, Kentaro Tsukida, Yasushi Iwakura, Yoichi Wada
  • Patent number: 11700467
    Abstract: A photoelectric conversion device of the present disclosure includes: a scanning unit; a first storage unit that stores a first setting value representing a setting of a first scan in response to an input from the outside; and a second storage unit that stores a second setting value representing a setting of a second scan in response to an input from the outside, wherein the scanning unit performs the first scan based on the first setting value and the second scan based on the second setting value in one frame period, and wherein both storing of the first setting value in the first storage unit and storing of the second setting value by the second storage unit are performed prior to a start of the first scan and a start of the second scan.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: July 11, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Noriyuki Shikina, Yoshiko Shigiya
  • Publication number: 20230209217
    Abstract: A photoelectric conversion apparatus comprising: pixels; L (L?3) vertical signal lines disposed on each pixel column; M (M?2) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line; a vertical scanning circuit configured to scan the selection circuits; and a control unit. The control unit sets first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs multiple read scanning operations at a time. In the first operation mode, the control unit uses first selection circuit out of the M selection circuits for scanning operation. In the second operation mode, the control unit uses a second selection circuit, which is different from the first selection circuit, out of the M selection circuits for scanning operation.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 29, 2023
    Inventors: Atsushi Shimada, Noriyuki Shikina, Yoshiko Shigiya
  • Patent number: 11627264
    Abstract: A photoelectric conversion device includes a pixel unit having pixels arranged to form rows and columns, each including a transfer transistor that transfers charge in a photoelectric converter to an output unit, and a pixel control unit that controls the pixels. The pixel control unit is configured to supply a control signal in accordance with an exposure period individually defined for pixel blocks of the pixel unit to pixels of each pixel block and read out, from each pixel, a first signal obtained when the photoelectric converter is in a reset state and a second signal based on charge accumulated in the photoelectric converter during the exposure period. A period excluding both the exposure period and a readout period of the second signal corresponds to a reset period of the photoelectric converter. The transfer transistor is off in a readout period of the first and second signals.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 11, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinya Igarashi, Noriyuki Shikina
  • Patent number: 11595606
    Abstract: A photoelectric conversion apparatus includes a pixel array having pixels arranged to form rows and columns and column signal lines configured to output noise signals and optical signals of the pixels, a driver configured to drive the pixels so that the optical signal is output following the noise signal from each pixel, A/D converters configured to perform A/D conversion to convert the noise signals output to the column signal lines into noise data and to subsequently perform A/D conversion to covert the optical signals output to the column signal lines into optical data, a data hold circuit, and a transmitter configured to transmit the noise data converted by the A/D converters to the data hold circuit and to subsequently transmit the optical data converted by the A/D converters to the data hold circuit.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: February 28, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Shikina, Yoshiko Shigiya, Shintaro Takenaka
  • Patent number: 11490041
    Abstract: The photoelectric conversion device includes a pixel unit configured to output first and second signals from columns of first and second regions, and a processing circuit including a first processing circuit including first and third memories, a second processing circuit including second and fourth memories, and a data exchange circuit. The first memory stores the first and second signals output from the first region, and the second memory stores the first and second signals output from the second region. The data exchange circuit stores the first signals read out from the first and second memories in the third memory, and stores the second signals read out from the first and second memories in the fourth memory. The processing circuit outputs the first signals stored in the third memory from the first processing circuit, and outputs the second signals stored in the fourth memory from the second processing circuit.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: November 1, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshiko Shigiya, Noriyuki Shikina, Shintaro Takenaka
  • Publication number: 20220210359
    Abstract: An apparatus includes a plurality of pixels, a comparator configured to compare an output signal of each of the plurality of pixels with a reference signal, and a counter of K bits (K is a natural number) configured to operate in parallel with operation of the comparator. The apparatus converts the output signal of each of the plurality of pixels into a digital signal using an output of the comparator and an output of the counter. The apparatus includes an addition unit configured to add a plurality of the digital signals. The addition unit includes a serial binary adder of M bits (M is a natural number less than K).
    Type: Application
    Filed: December 17, 2021
    Publication date: June 30, 2022
    Inventor: Noriyuki Shikina
  • Patent number: 11303829
    Abstract: Provided is an imaging device including a scanning unit configured to control a plurality of pixels so as to perform a shutter scan and a readout scan, and the scanning unit is further configured to switch a drive mode between a first drive mode and a second drive mode having periods of different lengths of the readout scan in control of the plurality of pixels and start the shutter scan performed in the second drive mode before the readout scan performed in the first drive mode ends when switching a drive mode from the first drive mode to the second drive mode.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 12, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshiko Shigiya, Noriyuki Shikina, Shintaro Takenaka
  • Publication number: 20220094875
    Abstract: A photoelectric conversion device of the present disclosure includes: a scanning unit; a first storage unit that stores a first setting value representing a setting of a first scan in response to an input from the outside; and a second storage unit that stores a second setting value representing a setting of a second scan in response to an input from the outside, wherein the scanning unit performs the first scan based on the first setting value and the second scan based on the second setting value in one frame period, and wherein both storing of the first setting value in the first storage unit and storing of the second setting value by the second storage unit are performed prior to a start of the first scan and a start of the second scan.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 24, 2022
    Inventors: Noriyuki Shikina, Yoshiko Shigiya
  • Publication number: 20220086383
    Abstract: The photoelectric conversion device includes a pixel unit configured to output first and second signals from columns of first and second regions, and a processing circuit including a first processing circuit including first and third memories, a second processing circuit including second and fourth memories, and a data exchange circuit. The first memory stores the first and second signals output from the first region, and the second memory stores the first and second signals output from the second region. The data exchange circuit stores the first signals read out from the first and second memories in the third memory, and stores the second signals read out from the first and second memories in the fourth memory. The processing circuit outputs the first signals stored in the third memory from the first processing circuit, and outputs the second signals stored in the fourth memory from the second processing circuit.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 17, 2022
    Inventors: Yoshiko Shigiya, Noriyuki Shikina, Shintaro Takenaka
  • Patent number: 11218661
    Abstract: A signal processing apparatus includes an analog-to-digital conversion unit, a determination unit including a comparator, and a data calculation unit that performs calculation. The data calculation unit generates a first calculation result by performing calculation including processing for averaging a first digital signal and a second digital signal or processing for adding the first and second digital signals. The data calculation unit generates a second calculation result based on a difference between the first digital signal and first noise digital data. The data calculation unit switches whether to output the first calculation result or output the second calculation result, based on a comparison result of the comparator.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 4, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsushi Shimada, Noriyuki Shikina, Shintaro Takenaka
  • Patent number: 11202023
    Abstract: An imaging device includes pixels, output lines on each column, an AD conversion unit including column AD conversion circuits connected to the output lines, a first storage unit including holding units connected to the column AD conversion circuits, a transfer unit that transfers signals in the first storage unit, a second storage unit that holds signals from the transfer unit, and an output unit that outputs signals in the second storage unit. The pixels output a first analog signal based on signal from the first photoelectric converter and a second analog signal based on signal from the first and second photoelectric converter. The AD conversion unit converts the first and second analog signals into first and second digital signals. The number of signals corresponding to the first digital signals of signals output by the output unit is less than the number of signals output in parallel from the output lines.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 14, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshiko Shigiya, Noriyuki Shikina, Shintaro Takenaka