Abstract: A startup check unit configured to check for a predetermined range of memory area is included. An operating system is started by using the memory area checked by the startup check unit. The operating system has a memory check unit configured to check for a memory area other than the memory area checked by the startup check unit, and an application startup unit configured to start an application depending on a memory amount indicating an amount of the memory area checked by the memory check unit.

Abstract: Information processing equipment of the present invention includes a proxy response processing unit which outputs a content of a response stored in association with a command to a storage unit, and a delay processing unit which sends commands to the storage unit in accordance with time stored in a memory unit, receives a response of the storage unit, determines whether or not there is a difference between the response and the stored response of the storage unit and, when there is a difference, updates the stored content of the response, then sets a value indicting an initialized state in a check flag which stores data indicating whether or not the storage unit is initialized, and a control unit which sends a command for the storage unit to the proxy response processing unit and sends a response of the storage unit to the delay processing unit.

Abstract: A startup check unit configured to check for a predetermined range of memory area is included. An operating system is started by using the memory area checked by the startup check unit. The operating system has a memory check unit configured to check for a memory area other than the memory area checked by the startup check unit, and an application startup unit configured to start an application depending on a memory amount indicating an amount of the memory area checked by the memory check unit.

Abstract: To provide a new operation verification method for an information processing flow, a central processing unit capable of building a plurality of virtual cores on a physical core includes: an element or part for executing, on an own virtual core, or causing another virtual core on the same physical core to execute, a reference instruction of directly referring to a current register value used by an arbitrary virtual core from the another virtual core without influence on an execution context of the arbitrary virtual core; and an element or part for switching a permission or authorization for executing the reference instruction of referring to the register value among the plurality of virtual cores.

Abstract: Information processing equipment of the present invention includes a proxy response processing unit which outputs a content of a response stored in association with a command to a storage unit, and a delay processing unit which sends commands to the storage unit in accordance with time stored in a memory unit, receives a response of the storage unit, determines whether or not there is a difference between the response and the stored response of the storage unit and, when there is a difference, updates the stored content of the response, then sets a value indicting an initialized state in a check flag which stores data indicating whether or not the storage unit is initialized, and a control unit which sends a command for the storage unit to the proxy response processing unit and sends a response of the storage unit to the delay processing unit.

Abstract: To provide a new operation verification method for an information processing flow, a central processing unit capable of building a plurality of virtual cores on a physical core includes: an element or part for executing, on an own virtual core, or causing another virtual core on the same physical core to execute, a reference instruction of directly referring to a current register value used by an arbitrary virtual core from the another virtual core without influence on an execution context of the arbitrary virtual core; and an element or part for switching a permission or authorization for executing the reference instruction of referring to the register value among the plurality of virtual cores.