Abstract: A computer system is described including a CPU core, a memory device storing non-cacheable data, and a bus interface unit (BIU) coupled between the CPU core and the memory device. The CPU core accesses the memory device via the BIU. The BIU includes a stream read buffer, and the system includes logic to determine when to enter a stream read buffer mode. includes a stream read buffer. Following at least one transaction accessing the non-cacheable data within the memory device, the BIU obtains a portion of the non-cacheable data from the memory device, and stores the portion within the stream read buffer. For example, the memory device may include multiple storage locations for storing the non-cacheable data, and the storage locations may have consecutive addresses. Following the least one transaction accessing the non-cacheable data, the BIU may obtain the contents of multiple, consecutively-addressed storage locations of the memory device, and store the contents within the stream read buffer.

Abstract: A system is disclosed for improving the efficiency of data transactions by permitting the length of burst transactions to be modified based upon system performance. A bus interface unit monitors the response times of memory devices, and, if WAIT periods are required before the memory device responds, the bus interface unit increases the length of the burst. Preferably, the bus interface unit includes a table of historical response times of various memory ranges, and determines an optimal burst length for each memory range. When a data transaction is made to a particular memory location, the BIU accesses the table and asserts a BURST signal for a sufficient period of time to accomplish the optimal burst length. After the optimal burst length has been reached in the existing memory transaction, the BURST signal is deasserted to end the burst cycle.