Patents by Inventor Norman J. Armendariz

Norman J. Armendariz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130271172
    Abstract: A probe tip may include a plurality of spaced projections adapted to contact the input/output lands of an integrated circuit device.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Norman J. Armendariz, Kay Chan Tong
  • Patent number: 8471577
    Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Margaret Simmons-Matthews, Jeff West
  • Patent number: 8344749
    Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: January 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Kenneth M. Butler, Margaret Simmons-Matthews
  • Publication number: 20110304349
    Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 15, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Margaret Simmons-Matthews, Jeff West
  • Publication number: 20110298488
    Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Kenneth M. Butler, Margaret Simmons-Matthews
  • Patent number: 6878305
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6875367
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 5, 2005
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6818155
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Publication number: 20040109974
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Application
    Filed: October 28, 2003
    Publication date: June 10, 2004
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Publication number: 20040087173
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 6, 2004
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Publication number: 20030121602
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 5828226
    Abstract: A probe card assembly includes a probe card, an interposer and a probe array. The probe array includes a plurality of closely spaced pins, each pin includes a post and a beam, and each beam has a first end attached to the top of a post and a second end for contacting an integrated circuit. A bead on the second end of the beam assures that the free end of the beam will contact an IC first. For contacts on a grid, the beams extend diagonally relative to the rows and columns of the grid, enabling the beams to be longer. For contacts in a row on centers closer than the pins, two rows of pins straddle the contacts and the beams extend toward the contacts from opposite sides of the contacts. The probe array can be formed on the high density side of the interposer.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: October 27, 1998
    Assignee: Cerprobe Corporation
    Inventors: H. Dan Higgins, Rajiv Pandey, Norman J. Armendariz, R. Dennis Bates