Patents by Inventor Norman W. Robson
Norman W. Robson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240184045Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an identification system, method of manufacture and method of use. The structure includes at least one waveguide structure and at least one damaged region positioned in a unique pattern on the at least one waveguide structure.Type: ApplicationFiled: December 6, 2022Publication date: June 6, 2024Inventors: Arpan DASGUPTA, Norman W. ROBSON, Danny MOY
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Patent number: 11367734Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.Type: GrantFiled: February 4, 2020Date of Patent: June 21, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Faraz Khan, Dan Moy, Norman W. Robson, Robert Katz, Darren L. Anand, Toshiaki Kirihata
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Publication number: 20210242230Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Inventors: Faraz KHAN, Dan MOY, Norman W. ROBSON, Robert KATZ, Darren L. ANAND, Toshiaki KIRIHATA
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Patent number: 10685705Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.Type: GrantFiled: July 27, 2018Date of Patent: June 16, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Faraz Khan, Norman W. Robson, Toshiaki Kirihata, Danny Moy, Darren L. Anand
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Publication number: 20200035295Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.Type: ApplicationFiled: July 27, 2018Publication date: January 30, 2020Inventors: Faraz KHAN, Norman W. ROBSON, Toshiaki KIRIHATA, Danny MOY, Darren L. ANAND
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Patent number: 9658255Abstract: According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.Type: GrantFiled: August 20, 2015Date of Patent: May 23, 2017Assignee: International Business Machines CorporationInventors: Mark A. DiRocco, Kirk D. Peterson, Norman W. Robson, Keith C. Stevens
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Patent number: 9372208Abstract: According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.Type: GrantFiled: January 2, 2014Date of Patent: June 21, 2016Assignee: International Business Machines CorporationInventors: Mark A. DiRocco, Kirk D. Peterson, Norman W. Robson, Keith C. Stevens
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Publication number: 20150362534Abstract: According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.Type: ApplicationFiled: August 20, 2015Publication date: December 17, 2015Inventors: Mark A. DiRocco, Kirk D. Peterson, Norman W. Robson, Keith C. Stevens
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Circuits for self-reconfiguration or intrinsic functional changes of chips before vs. after stacking
Patent number: 9194912Abstract: A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack.Type: GrantFiled: November 29, 2012Date of Patent: November 24, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norman W. Robson, Daniel J. Fainstein -
Publication number: 20150185273Abstract: According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Mark A. DiRocco, Kirk D. Peterson, Norman W. Robson, Keith C. Stevens
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Patent number: 8975910Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.Type: GrantFiled: April 27, 2012Date of Patent: March 10, 2015Assignee: International Business Machines CorporationInventors: Troy L. Graves-Abe, Benjamin A. Himmel, Chandrasekharan Kothandaraman, Norman W. Robson
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CIRCUITS FOR SELF-RECONFIGURATION OR INTRINSIC FUNCTIONAL CHANGES OF CHIPS BEFORE VS. AFTER STACKING
Publication number: 20140145750Abstract: A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack.Type: ApplicationFiled: November 29, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norman W. Robson, Daniel J. Fainstein -
Patent number: 8629049Abstract: A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.Type: GrantFiled: March 15, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Patent number: 8590010Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.Type: GrantFiled: November 22, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Daniel J. Fainstein, Alberto Cestero, Subramanian S. Iyer, Toshiaki Kirihata, Norman W. Robson, Sami Rosenblatt
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Publication number: 20130285694Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy L. Graves-Abe, Benjamin A. Himmel, Chandrasekharan Kothandaraman, Norman W. Robson
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Patent number: 8569755Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.Type: GrantFiled: September 13, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Patent number: 8519507Abstract: An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.Type: GrantFiled: June 29, 2009Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Publication number: 20130133031Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: International Business Machines CorporationInventors: Daniel J. Fainstein, Alberto Cestero, Subramanian S. Iyer, Toshiaki Kirihata, Norman W. Robson, Sami Rosenblatt
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Publication number: 20130063202Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.Type: ApplicationFiled: September 13, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Patent number: 8350264Abstract: An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region.Type: GrantFiled: July 14, 2010Date of Patent: January 8, 2013Assignee: International Businesss Machines CorporationInventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran