Abstract: A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.

Abstract: A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cycle, the memory controller disables the main data memories on the module, and allows the maintenance bus to read or write data to these memories.

Abstract: In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.

Abstract: A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.

Abstract: A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.

Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.

Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.

Abstract: A printed circuit board includes a rectangular array of substantially equally spaced rows and columns of surface mount connectors which are fixedly held to the board by means of cross-shaped connector holders which are disposed at the intersections of the rows and columns. In this fashion, there is achieved a substantial reduction in the number of holes which must be provided in the printed circuit board for connector attachment. This greatly facilitates wiring placement on printed circuit boards, particularly multi-layer boards.