Abstract: Systems and methods for channel pairing a transmitter and a receiver are provided. In this regard, a representative method, among others, includes selecting a channel in a radio frequency (RF) band; transmitting a carrier and alert tone on the selected channel in the RF band; responsive to detecting the transmitted carrier and alert tone, demodulating the carrier and alert tone on the selected channel in the RF band and producing the demodulated alert tone; and responsive to detecting the produced alert tone, using the selected channel to establish a wireless link between the transmitter and receiver.

Abstract: Systems and methods for mitigating multipath signals in a receiver are provided. In this regard, a representative system, among others, includes a radio frequency (RF) front-end and at least one analog-to-digital converter (ADC). The RF front-end receives FM signals and down-converts the received frequency signals to intermediate frequency (IF) signals. The analog-to-digital converter (ADC) receives the intermediate frequency signals and digitizes multiple FM channels around a desired FM channel associated with the down-converted signals. The system further includes multiple sets of digital processing components that are configured to simultaneously receive and process the digitized multiple channels. The multiple sets of digital processing components include at least two parallel channel selection and demodulation paths in which the respective digitized multiple channels are processed therethrough.

Abstract: A Radio Frequency Receiver on a Single Integrated Circuit (“RFSIC”) is described. The RFSIC may include a mixer, a phase-locked loop (“PLL”) in signal communication with the mixer, and an on-chip auto-tuned RF filter in signal communication with both the mixer and PPL, such that the same PLL simultaneously tunes the frequency of the VCO and the frequency response of the auto-tuned RF filter.

Abstract: An RF-to-IF converter includes radio frequency (RF) to intermediate frequency (IF) processing circuitry and a frequency synthesizer for generating a local oscillator signal and clocking signals. The frequency synthesizer includes a local oscillator (LO) output coupled to the processing circuitry, a baseband processor clock output, and clock generation circuitry for generating a baseband processor clock with a frequency of approximately 48 fo on the baseband processor clock output, where fo is 1.023 MHz.

Abstract: A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block.

Abstract: A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block.

Abstract: Multi-band or wideband impedance matching in RF amplifiers is disclosed, using variable negative feedback. The feedback is provided by variable impedance connected between the input and output terminals of an inverting amplifier, which may be single-ended, or differential. The variable impedance is used in conjunction with a fixed input impedance matching network to tune the variable impedance to different frequencies. The variable impedance feedback can also be used for gain control, and has the added benefit of stabilizing the amplifier. Both multi-band and wideband amplification can be optimized through the use of the disclosed circuitry and techniques. Use of an output impedance matching network in conjunction with the RF amplifier is optional.

Abstract: A reconfigurable downconverter (10) for a multi-band positioning receiver is operable with an RF synthesizer (18) with fixed output frequency, and a fixed wideband RF input (28). The downconverter (10) includes an RF mixer (12) operable to accept a range of frequencies that encompass the GPS and Galileo frequency bands and to output a downconverted IF signal (32). A fixed frequency local oscillator signal (34) is coupled to the RF mixer (12). At least one IF processor 14 further downconverts the downconverted IF signal (32) to at least one baseband signal (22). At least one of the IF processors (14) is reconfigurable for different frequency bands.

Abstract: In a system and method for simultaneously receiving or switching between dual frequency carrier signals in a GPS receiver, the GPS receiver is adapted to utilize different harmonics of a sub-harmonic frequency generator, which may include a lower frequency voltage controlled oscillator (VCO) to detect the L1 and L2 GPS carriers. A sub-harmonic mixer may be used to simultaneously down convert the L1 and L2 signals to a lower intermediate frequency (IF). A second mixer may be an image reject (IR) mixer used to separate the downconverted L1 and L2 signals. This mixer may be configured to simultaneously monitor the L1 and L2 signals, or to switch between the L1 and L2 signals. High frequency switching is not required of the radio frequency (RF) input or local oscillator signals, and simultaneous L1 and L2 reception is enabled without and 3 dB image noise degradation.

Abstract: A GPS RF Front End IC containing a Programmable Frequency Synthesizer is disclosed. The GPS RF front end IC having a programmable frequency synthesizer allows a relatively fixed internal frequency plan while able to use a number of different reference frequencies provided by the host platform, which can be a wireless phone, or other such device, which can provide an accurate reference frequency signal.

Abstract: An RF-to-IF converter includes radio frequency (RF) to intermediate frequency (IF) processing circuitry and a frequency synthesizer for generating a local oscillator signal and clocking signals. The frequency synthesizer includes a local oscillator (LO) output coupled to the processing circuitry, a baseband processor clock output, and clock generation circuitry for generating a baseband processor clock with a frequency of approximately 48 fo on the baseband processor clock output, where fo is 1.023 MHz.

Abstract: A fractional-R synthesizer having a divider (406) with rational increments and configurable in rational steps able to generate a plurality of frequencies in rational increments from a reference frequency. The fractional-R synthesizer is included in the feedback loop of a PLL. Preferably a Delta-Sigma modulator (412) is responsive to an input representing a fractional value and clocked by the output of said divider (406) to produce an output signal that modulates the divide ratio of the variable rational divider (406).