Abstract: This non-volatile multi-state memory device switches a storing resolution of multi-state data corresponding to digital data stored in a non-volatile memory cell according to the data's characteristics. In more detail, digital audio data are output from an ADPCM encoder in n-bit units and m bits of address data indicating an address at which audio data are stored are output from an address controller. These are then input to a switching circuit, a bit number converting circuit converts m bits of address data to n bits of address data at the same level as the m bit data, and the converted n bits of address data and n bits of audio data are inputted to a second multiplexer. An output of the Second multiplexer is then selected in compliance with a switch signal from the address controller and either the selected n bits of address data or the audio data are sent to a read-write circuit.

Abstract: Inputted digital data are held in a data register and converted to multi-state analog amount by a resistance dividing circuit and a decoder. A comparator compares an analog amount read from a non-volatile memory cell with a converted analog amount; and in accordance with this comparison result, a writing voltage is supplied to a memory cell. A first bias generating circuit is provided for generating two different types of bias voltages as this writing voltage, MOS transistors are inserted as respective switches to the bias voltage supply lines and writing voltages are switched by selectively ON/OFF-controlling one of the MOS transistors in accordance with the upper bit of the inputted digital data. As a result, unnecessary writing time can be eliminated, time required for executing writing can be reduced and circuit configuration can be simplified.

Abstract: A data register for holding input digital data, a resistance dividing circuit for generating a plurality of analog voltages, a decoder for decoding the data of the data register and selectively outputting one of a plurality of analog voltages and a comparator for comparing this decoded output with an analog amount read from a memory cell are provided. In write mode, this memory device sets data to be written in the data register and writes an analog amount corresponding to the set data in the memory cell, in read mode, the apparatus sequentially sets in the data register digital data updated in sequence from a designated value, executes comparison at the comparator for each setting and terminates the digital data setting in response to the comparison result at the data register, thus digital data corresponding to the analog amount read from the memory cell is thereby obtained at the data register. As a result, circuit configuration can be simplified and circuit scale reduced.